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llvm-project/llvm/test/CodeGen/ARM/scavenging.mir

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[ARM] Remove FeatureNoARM implies ModeThumb. Summary: By removing FeatureNoARM implies ModeThumb, we can detect cases where a function's target-features contain -thumb-mode (enables ARM codegen for the function), but the architecture does not support ARM mode. Previously, the implication caused the FeatureNoARM bit to be cleared for functions with -thumb-mode, making the assertion in ARMSubtarget::ARMSubtarget [1] pointless for such functions. This assertion is the only guard against generating ARM code for architectures without ARM codegen support. Is there a place where we could easily generate error messages for the user? At the moment, we would generate ARM code for Thumb-only architectures. X86 has the same behavior as ARM, as in it only has an assertion and no error message, but I think for ARM an error message would be helpful. What do you think? For the example below, `llc -mtriple=armv7m-eabi test.ll -o -` will generate ARM assembler (or fail with an assertion error with this patch). Note that if we run the resulting assembler through llvm-mc, we get an appropriate error message, but not when codegen is handled through clang. ``` define void @bar() #0 { entry: ret void } attributes #0 = { "target-features"="-thumb-mode" } ``` [1] https://github.com/llvm-mirror/llvm/blob/c1f7b54cef62e9c8aa745d40bea146a167bf844e/lib/Target/ARM/ARMSubtarget.cpp#L147 Reviewers: t.p.northover, rengolin, peter.smith, aadg, silviu.baranga, richard.barton.arm, echristo Reviewed By: rengolin, echristo Subscribers: efriedma, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35569 llvm-svn: 310476
2017-08-09 21:53:28 +08:00
# RUN: llc -o - %s -mtriple=thumb-arm-none-eabi -mcpu=cortex-m0 -run-pass scavenger-test | FileCheck %s
RegisterScavenging: Fix PR33687 When scavenging for a use in instruction MI, we will reload after that instruction and hence cannot spill uses/defs of this instruction. This fixes http://llvm.org/PR33687 llvm-svn: 307352
2017-07-07 11:02:18 +08:00
---
# CHECK-LABEL: name: scavengebug0
# Make sure we are not spilling/using a physreg used in the very last
# instruction of the scavenging range.
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
# CHECK-NOT: tSTRi {{.*}}$r0,{{.*}}$r0
# CHECK-NOT: tSTRi {{.*}}$r1,{{.*}}$r1
# CHECK-NOT: tSTRi {{.*}}$r2,{{.*}}$r2
# CHECK-NOT: tSTRi {{.*}}$r3,{{.*}}$r3
# CHECK-NOT: tSTRi {{.*}}$r4,{{.*}}$r4
# CHECK-NOT: tSTRi {{.*}}$r5,{{.*}}$r5
# CHECK-NOT: tSTRi {{.*}}$r6,{{.*}}$r6
# CHECK-NOT: tSTRi {{.*}}$r7,{{.*}}$r7
RegisterScavenging: Fix PR33687 When scavenging for a use in instruction MI, we will reload after that instruction and hence cannot spill uses/defs of this instruction. This fixes http://llvm.org/PR33687 llvm-svn: 307352
2017-07-07 11:02:18 +08:00
name: scavengebug0
body: |
bb.0:
; Bring up register pressure to force emergency spilling
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
$r0 = IMPLICIT_DEF
$r1 = IMPLICIT_DEF
$r2 = IMPLICIT_DEF
$r3 = IMPLICIT_DEF
$r4 = IMPLICIT_DEF
$r5 = IMPLICIT_DEF
$r6 = IMPLICIT_DEF
$r7 = IMPLICIT_DEF
RegisterScavenging: Fix PR33687 When scavenging for a use in instruction MI, we will reload after that instruction and hence cannot spill uses/defs of this instruction. This fixes http://llvm.org/PR33687 llvm-svn: 307352
2017-07-07 11:02:18 +08:00
%0 : tgpr = IMPLICIT_DEF
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
%0 = tADDhirr %0, $sp, 14, $noreg
tSTRi $r0, %0, 0, 14, $noreg
RegisterScavenging: Fix PR33687 When scavenging for a use in instruction MI, we will reload after that instruction and hence cannot spill uses/defs of this instruction. This fixes http://llvm.org/PR33687 llvm-svn: 307352
2017-07-07 11:02:18 +08:00
%1 : tgpr = IMPLICIT_DEF
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
%1 = tADDhirr %1, $sp, 14, $noreg
tSTRi $r1, %1, 0, 14, $noreg
RegisterScavenging: Fix PR33687 When scavenging for a use in instruction MI, we will reload after that instruction and hence cannot spill uses/defs of this instruction. This fixes http://llvm.org/PR33687 llvm-svn: 307352
2017-07-07 11:02:18 +08:00
%2 : tgpr = IMPLICIT_DEF
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
%2 = tADDhirr %2, $sp, 14, $noreg
tSTRi $r2, %2, 0, 14, $noreg
RegisterScavenging: Fix PR33687 When scavenging for a use in instruction MI, we will reload after that instruction and hence cannot spill uses/defs of this instruction. This fixes http://llvm.org/PR33687 llvm-svn: 307352
2017-07-07 11:02:18 +08:00
%3 : tgpr = IMPLICIT_DEF
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
%3 = tADDhirr %3, $sp, 14, $noreg
tSTRi $r3, %3, 0, 14, $noreg
RegisterScavenging: Fix PR33687 When scavenging for a use in instruction MI, we will reload after that instruction and hence cannot spill uses/defs of this instruction. This fixes http://llvm.org/PR33687 llvm-svn: 307352
2017-07-07 11:02:18 +08:00
%4 : tgpr = IMPLICIT_DEF
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
%4 = tADDhirr %4, $sp, 14, $noreg
tSTRi $r4, %4, 0, 14, $noreg
RegisterScavenging: Fix PR33687 When scavenging for a use in instruction MI, we will reload after that instruction and hence cannot spill uses/defs of this instruction. This fixes http://llvm.org/PR33687 llvm-svn: 307352
2017-07-07 11:02:18 +08:00
%5 : tgpr = IMPLICIT_DEF
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
%5 = tADDhirr %5, $sp, 14, $noreg
tSTRi $r5, %5, 0, 14, $noreg
RegisterScavenging: Fix PR33687 When scavenging for a use in instruction MI, we will reload after that instruction and hence cannot spill uses/defs of this instruction. This fixes http://llvm.org/PR33687 llvm-svn: 307352
2017-07-07 11:02:18 +08:00
%6 : tgpr = IMPLICIT_DEF
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
%6 = tADDhirr %6, $sp, 14, $noreg
tSTRi $r6, %6, 0, 14, $noreg
RegisterScavenging: Fix PR33687 When scavenging for a use in instruction MI, we will reload after that instruction and hence cannot spill uses/defs of this instruction. This fixes http://llvm.org/PR33687 llvm-svn: 307352
2017-07-07 11:02:18 +08:00
%7 : tgpr = IMPLICIT_DEF
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
%7 = tADDhirr %7, $sp, 14, $noreg
tSTRi $r7, %7, 0, 14, $noreg
RegisterScavenging: Fix PR33687 When scavenging for a use in instruction MI, we will reload after that instruction and hence cannot spill uses/defs of this instruction. This fixes http://llvm.org/PR33687 llvm-svn: 307352
2017-07-07 11:02:18 +08:00
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
KILL $r0
KILL $r1
KILL $r2
KILL $r3
KILL $r4
KILL $r5
KILL $r6
KILL $r7