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llvm-project/llvm/test/CodeGen/ARM/2012-08-30-select.ll

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Currently targets that do not support selects with scalar conditions and vector operands - scalarize the code. ARM is such a target because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 llvm-svn: 162926
2012-08-31 03:17:29 +08:00
; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
; rdar://12201387
;CHECK: select_s_v_v
Generate better select code by allowing the target to use scalar select, and not sign-extend. llvm-svn: 163086
2012-09-02 16:20:07 +08:00
;CHECK: it eq
;CHECK-NEXT: moveq.w r2, #-1
Currently targets that do not support selects with scalar conditions and vector operands - scalarize the code. ARM is such a target because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 llvm-svn: 162926
2012-08-31 03:17:29 +08:00
;CHECK: vbsl
;CHECK: bx
define <16 x i8> @select_s_v_v(i32 %avail, i8* %bar) {
entry:
%vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %bar, i32 1)
%and = and i32 %avail, 1
%tobool = icmp eq i32 %and, 0
%vld1. = select i1 %tobool, <16 x i8> %vld1, <16 x i8> zeroinitializer
ret <16 x i8> %vld1.
}
declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* , i32 )