forked from OSchip/llvm-project
19 lines
545 B
TableGen
19 lines
545 B
TableGen
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// RUN: not llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
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include "llvm/Target/Target.td"
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def TestTarget : Target;
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// CHECK: [[FILE]]:[[@LINE+1]]:1: error: No schedule information for instruction 'TestInst' in SchedMachineModel 'TestSchedModel'
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def TestInst : Instruction {
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let OutOperandList = (outs);
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let InOperandList = (ins);
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bits<8> Inst = 0b00101010;
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}
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def TestSchedModel : SchedMachineModel {
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let CompleteModel = 1;
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}
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def TestProcessor : ProcessorModel<"testprocessor", TestSchedModel, []>;
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