[ELF] - Implemented support for test/binop relaxations from latest ABI.
Patch implements next relaxation from latest ABI:
"Convert memory operand of test and binop into immediate operand, where binop is one of adc, add, and, cmp, or,
sbb, sub, xor instructions, when position-independent code is disabled."
It is described in System V Application Binary Interface AMD64 Architecture Processor
Supplement Draft Version 0.99.8 (https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-r249.pdf,
B.2 "B.2 Optimize GOTPCRELX Relocations").
Differential revision: http://reviews.llvm.org/D20793
llvm-svn: 271405
2016-06-02 00:45:30 +08:00
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# REQUIRES: x86
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# RUN: llvm-mc -filetype=obj -relax-relocations -triple=x86_64-unknown-linux %s -o %t.o
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# RUN: ld.lld %t.o -o %t1
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# RUN: llvm-readobj -symbols -r %t1 | FileCheck --check-prefix=SYMRELOC %s
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# RUN: llvm-objdump -d %t1 | FileCheck --check-prefix=DISASM %s
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## There is no relocations.
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# SYMRELOC: Relocations [
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# SYMRELOC-NEXT: ]
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# SYMRELOC: Symbols [
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# SYMRELOC: Symbol {
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# SYMRELOC: Name: bar
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2016-11-24 01:44:02 +08:00
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# SYMRELOC-NEXT: Value: 0x202000
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[ELF] - Implemented support for test/binop relaxations from latest ABI.
Patch implements next relaxation from latest ABI:
"Convert memory operand of test and binop into immediate operand, where binop is one of adc, add, and, cmp, or,
sbb, sub, xor instructions, when position-independent code is disabled."
It is described in System V Application Binary Interface AMD64 Architecture Processor
Supplement Draft Version 0.99.8 (https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-r249.pdf,
B.2 "B.2 Optimize GOTPCRELX Relocations").
Differential revision: http://reviews.llvm.org/D20793
llvm-svn: 271405
2016-06-02 00:45:30 +08:00
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2016-11-24 01:44:02 +08:00
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## 2105344 = 0x202000 (bar)
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[ELF] - Implemented support for test/binop relaxations from latest ABI.
Patch implements next relaxation from latest ABI:
"Convert memory operand of test and binop into immediate operand, where binop is one of adc, add, and, cmp, or,
sbb, sub, xor instructions, when position-independent code is disabled."
It is described in System V Application Binary Interface AMD64 Architecture Processor
Supplement Draft Version 0.99.8 (https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-r249.pdf,
B.2 "B.2 Optimize GOTPCRELX Relocations").
Differential revision: http://reviews.llvm.org/D20793
llvm-svn: 271405
2016-06-02 00:45:30 +08:00
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# DISASM: Disassembly of section .text:
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# DISASM-NEXT: _start:
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2016-11-24 01:44:02 +08:00
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# DISASM-NEXT: 201000: {{.*}} adcq $2105344, %rax
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# DISASM-NEXT: 201007: {{.*}} addq $2105344, %rbx
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# DISASM-NEXT: 20100e: {{.*}} andq $2105344, %rcx
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# DISASM-NEXT: 201015: {{.*}} cmpq $2105344, %rdx
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# DISASM-NEXT: 20101c: {{.*}} orq $2105344, %rdi
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# DISASM-NEXT: 201023: {{.*}} sbbq $2105344, %rsi
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# DISASM-NEXT: 20102a: {{.*}} subq $2105344, %rbp
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# DISASM-NEXT: 201031: {{.*}} xorq $2105344, %r8
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# DISASM-NEXT: 201038: {{.*}} testq $2105344, %r15
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[ELF] - Implemented support for test/binop relaxations from latest ABI.
Patch implements next relaxation from latest ABI:
"Convert memory operand of test and binop into immediate operand, where binop is one of adc, add, and, cmp, or,
sbb, sub, xor instructions, when position-independent code is disabled."
It is described in System V Application Binary Interface AMD64 Architecture Processor
Supplement Draft Version 0.99.8 (https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-r249.pdf,
B.2 "B.2 Optimize GOTPCRELX Relocations").
Differential revision: http://reviews.llvm.org/D20793
llvm-svn: 271405
2016-06-02 00:45:30 +08:00
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# RUN: ld.lld -shared %t.o -o %t2
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2016-08-31 16:51:39 +08:00
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# RUN: llvm-readobj -s -r -d %t2 | FileCheck --check-prefix=SEC-PIC %s
|
[ELF] - Implemented support for test/binop relaxations from latest ABI.
Patch implements next relaxation from latest ABI:
"Convert memory operand of test and binop into immediate operand, where binop is one of adc, add, and, cmp, or,
sbb, sub, xor instructions, when position-independent code is disabled."
It is described in System V Application Binary Interface AMD64 Architecture Processor
Supplement Draft Version 0.99.8 (https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-r249.pdf,
B.2 "B.2 Optimize GOTPCRELX Relocations").
Differential revision: http://reviews.llvm.org/D20793
llvm-svn: 271405
2016-06-02 00:45:30 +08:00
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# RUN: llvm-objdump -d %t2 | FileCheck --check-prefix=DISASM-PIC %s
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# SEC-PIC: Section {
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# SEC-PIC: Index:
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# SEC-PIC: Name: .got
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# SEC-PIC-NEXT: Type: SHT_PROGBITS
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# SEC-PIC-NEXT: Flags [
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# SEC-PIC-NEXT: SHF_ALLOC
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# SEC-PIC-NEXT: SHF_WRITE
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# SEC-PIC-NEXT: ]
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2017-01-10 09:21:30 +08:00
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# SEC-PIC-NEXT: Address: 0x30A0
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# SEC-PIC-NEXT: Offset: 0x30A0
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[ELF] - Implemented support for test/binop relaxations from latest ABI.
Patch implements next relaxation from latest ABI:
"Convert memory operand of test and binop into immediate operand, where binop is one of adc, add, and, cmp, or,
sbb, sub, xor instructions, when position-independent code is disabled."
It is described in System V Application Binary Interface AMD64 Architecture Processor
Supplement Draft Version 0.99.8 (https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-r249.pdf,
B.2 "B.2 Optimize GOTPCRELX Relocations").
Differential revision: http://reviews.llvm.org/D20793
llvm-svn: 271405
2016-06-02 00:45:30 +08:00
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# SEC-PIC-NEXT: Size: 8
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# SEC-PIC-NEXT: Link:
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# SEC-PIC-NEXT: Info:
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# SEC-PIC-NEXT: AddressAlignment:
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# SEC-PIC-NEXT: EntrySize:
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# SEC-PIC-NEXT: }
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2016-08-31 16:51:39 +08:00
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# SEC-PIC: Relocations [
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# SEC-PIC-NEXT: Section ({{.*}}) .rela.dyn {
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2017-01-10 09:21:30 +08:00
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# SEC-PIC-NEXT: 0x30A0 R_X86_64_RELATIVE - 0x2000
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2016-08-31 16:51:39 +08:00
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# SEC-PIC-NEXT: }
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# SEC-PIC-NEXT: ]
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2016-10-06 04:09:50 +08:00
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# SEC-PIC: 0x000000006FFFFFF9 RELACOUNT 1
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[ELF] - Implemented support for test/binop relaxations from latest ABI.
Patch implements next relaxation from latest ABI:
"Convert memory operand of test and binop into immediate operand, where binop is one of adc, add, and, cmp, or,
sbb, sub, xor instructions, when position-independent code is disabled."
It is described in System V Application Binary Interface AMD64 Architecture Processor
Supplement Draft Version 0.99.8 (https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-r249.pdf,
B.2 "B.2 Optimize GOTPCRELX Relocations").
Differential revision: http://reviews.llvm.org/D20793
llvm-svn: 271405
2016-06-02 00:45:30 +08:00
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## Check that there was no relaxation performed. All values refer to got entry.
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2016-08-31 16:51:39 +08:00
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## Ex: 0x1000 + 4249 + 7 = 0x20A0
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## 0x102a + 4207 + 7 = 0x20A0
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[ELF] - Implemented support for test/binop relaxations from latest ABI.
Patch implements next relaxation from latest ABI:
"Convert memory operand of test and binop into immediate operand, where binop is one of adc, add, and, cmp, or,
sbb, sub, xor instructions, when position-independent code is disabled."
It is described in System V Application Binary Interface AMD64 Architecture Processor
Supplement Draft Version 0.99.8 (https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-r249.pdf,
B.2 "B.2 Optimize GOTPCRELX Relocations").
Differential revision: http://reviews.llvm.org/D20793
llvm-svn: 271405
2016-06-02 00:45:30 +08:00
|
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# DISASM-PIC: Disassembly of section .text:
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# DISASM-PIC-NEXT: _start:
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2017-01-10 09:21:30 +08:00
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# DISASM-PIC-NEXT: 1000: {{.*}} adcq 8345(%rip), %rax
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# DISASM-PIC-NEXT: 1007: {{.*}} addq 8338(%rip), %rbx
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# DISASM-PIC-NEXT: 100e: {{.*}} andq 8331(%rip), %rcx
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# DISASM-PIC-NEXT: 1015: {{.*}} cmpq 8324(%rip), %rdx
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# DISASM-PIC-NEXT: 101c: {{.*}} orq 8317(%rip), %rdi
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# DISASM-PIC-NEXT: 1023: {{.*}} sbbq 8310(%rip), %rsi
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# DISASM-PIC-NEXT: 102a: {{.*}} subq 8303(%rip), %rbp
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# DISASM-PIC-NEXT: 1031: {{.*}} xorq 8296(%rip), %r8
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# DISASM-PIC-NEXT: 1038: {{.*}} testq 8289(%rip), %r15
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[ELF] - Implemented support for test/binop relaxations from latest ABI.
Patch implements next relaxation from latest ABI:
"Convert memory operand of test and binop into immediate operand, where binop is one of adc, add, and, cmp, or,
sbb, sub, xor instructions, when position-independent code is disabled."
It is described in System V Application Binary Interface AMD64 Architecture Processor
Supplement Draft Version 0.99.8 (https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-r249.pdf,
B.2 "B.2 Optimize GOTPCRELX Relocations").
Differential revision: http://reviews.llvm.org/D20793
llvm-svn: 271405
2016-06-02 00:45:30 +08:00
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.data
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.type bar, @object
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bar:
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.byte 1
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.size bar, .-bar
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.text
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.globl _start
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.type _start, @function
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_start:
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adcq bar@GOTPCREL(%rip), %rax
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addq bar@GOTPCREL(%rip), %rbx
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andq bar@GOTPCREL(%rip), %rcx
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cmpq bar@GOTPCREL(%rip), %rdx
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orq bar@GOTPCREL(%rip), %rdi
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sbbq bar@GOTPCREL(%rip), %rsi
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subq bar@GOTPCREL(%rip), %rbp
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xorq bar@GOTPCREL(%rip), %r8
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testq %r15, bar@GOTPCREL(%rip)
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