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llvm-project/llvm/lib/Target/Mips/MipsSEISelLowering.h

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[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// Subclass of MipsTargetLowering specialized for mips32/64.
//
//===----------------------------------------------------------------------===//
Canonicalize header guards into a common format. Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
2014-08-14 00:26:38 +08:00
#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
#include "MipsISelLowering.h"
[mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is called in several places in ScheduleDAGRRList.cpp. llvm-svn: 178393
2013-03-30 09:12:05 +08:00
#include "MipsRegisterInfo.h"
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
namespace llvm {
class MipsSETargetLowering : public MipsTargetLowering {
public:
In preparation for replacing the whole subtarget on the target machine, have target lowering take the subtarget explicitly. llvm-svn: 213426
2014-07-19 07:25:04 +08:00
explicit MipsSETargetLowering(MipsTargetMachine &TM,
const MipsSubtarget &STI);
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal llvm-svn: 191191
2013-09-23 20:02:46 +08:00
/// \brief Enable MSA support for the given integer type and Register
/// class.
[mips][msa] Separate the configuration of int/float vector types since they will diverge soon No functional change llvm-svn: 190506
2013-09-11 18:15:48 +08:00
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal llvm-svn: 191191
2013-09-23 20:02:46 +08:00
/// \brief Enable MSA support for the given floating-point type and
/// Register class.
[mips][msa] Separate the configuration of int/float vector types since they will diverge soon No functional change llvm-svn: 190506
2013-09-11 18:15:48 +08:00
void addMSAFloatType(MVT::SimpleValueType Ty,
const TargetRegisterClass *RC);
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
Add alignment value to allowsUnalignedMemoryAccess Rename to allowsMisalignedMemoryAccess. On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment, and don't need to be split into multiple accesses. Vector loads with an alignment of the element type are not uncommon in OpenCL code. llvm-svn: 214055
2014-07-28 01:46:40 +08:00
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS = 0,
unsigned Align = 1,
bool *Fast = nullptr) const override;
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions. The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. llvm-svn: 178403
2013-03-30 09:36:35 +08:00
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
[mips] Move the code which does dag-combine for multiply-add/sub nodes to derived class MipsSETargetLowering. We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16 doesn't have support for multipy-add/sub instructions. llvm-svn: 178404
2013-03-30 09:42:24 +08:00
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) const override;
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
EVT VT) const override {
[mips] Override TargetLoweringBase::isShuffleMaskLegal. llvm-svn: 179433
2013-04-13 08:45:02 +08:00
return false;
}
So that we can include target lowering in the subtarget, remove include circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
2014-07-03 07:18:40 +08:00
const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
[mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is called in several places in ScheduleDAGRRList.cpp. llvm-svn: 178393
2013-03-30 09:12:05 +08:00
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
private:
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
unsigned NextStackOffset,
const MipsFunctionInfo& FI) const override;
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
void
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
getOpndList(SmallVectorImpl<SDValue> &Ops,
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
CallLoweringInfo &CLI, SDValue Callee,
SDValue Chain) const override;
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions. The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. llvm-svn: 178403
2013-03-30 09:36:35 +08:00
SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
SelectionDAG &DAG) const;
[mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN and lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering. No functionality changes. llvm-svn: 179444
2013-04-13 10:13:30 +08:00
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
[mips][msa] Added load/store intrinsics. llvm-svn: 189476
2013-08-28 20:04:29 +08:00
SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal llvm-svn: 191191
2013-09-23 20:02:46 +08:00
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
[mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics) llvm-svn: 191301
2013-09-24 22:02:15 +08:00
/// \brief Lower VECTOR_SHUFFLE into one of a number of instructions
/// depending on the indices in the shuffle.
SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
[mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN and lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering. No functionality changes. llvm-svn: 179444
2013-04-13 10:13:30 +08:00
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
MachineBasicBlock *BB) const;
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
MachineBasicBlock *BB,
unsigned BranchOp) const;
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. llvm-svn: 191514
2013-09-27 20:17:32 +08:00
/// \brief Emit the COPY_FW pseudo instruction
MachineBasicBlock *emitCOPY_FW(MachineInstr *MI,
MachineBasicBlock *BB) const;
/// \brief Emit the COPY_FD pseudo instruction
MachineBasicBlock *emitCOPY_FD(MachineInstr *MI,
MachineBasicBlock *BB) const;
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
2013-09-27 20:31:32 +08:00
/// \brief Emit the INSERT_FW pseudo instruction
MachineBasicBlock *emitINSERT_FW(MachineInstr *MI,
MachineBasicBlock *BB) const;
/// \brief Emit the INSERT_FD pseudo instruction
MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
MachineBasicBlock *BB) const;
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
2014-04-30 20:09:32 +08:00
/// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI,
MachineBasicBlock *BB,
unsigned EltSizeInBytes,
bool IsFP) const;
[mips][msa] Added support for build_vector for v4f32 and v2f64. llvm-svn: 192699
2013-10-15 21:14:41 +08:00
/// \brief Emit the FILL_FW pseudo instruction
MachineBasicBlock *emitFILL_FW(MachineInstr *MI,
MachineBasicBlock *BB) const;
/// \brief Emit the FILL_FD pseudo instruction
MachineBasicBlock *emitFILL_FD(MachineInstr *MI,
MachineBasicBlock *BB) const;
[mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics) llvm-svn: 193239
2013-10-23 18:36:52 +08:00
/// \brief Emit the FEXP2_W_1 pseudo instructions.
MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI,
MachineBasicBlock *BB) const;
/// \brief Emit the FEXP2_D_1 pseudo instructions.
MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI,
MachineBasicBlock *BB) const;
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
};
}
Canonicalize header guards into a common format. Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
2014-08-14 00:26:38 +08:00
#endif