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llvm-project/llvm/test/MachineVerifier/verifier-phi.mir

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Add missing triple args to tests llvm-svn: 319686
2017-12-05 04:08:28 +08:00
# RUN: llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none | FileCheck %s
Try to organize MachineVerifier tests The Verifier is separate from the MachineVerifier, so move it to a different directory. Some other verifier tests were scattered in target codegen tests as well (although I'm sure I missed some). Work towards using a more consistent naming scheme to make it clearer where the gaps still are for generic instructions. llvm-svn: 354138
2019-02-15 23:24:31 +08:00
# REQUIRES: x86-registered-target
MachineVerifier: undef phi arg doesn't need to be live-out from predecessor Differential Revision: https://reviews.llvm.org/D40756 llvm-svn: 319674
2017-12-05 02:57:48 +08:00
# This should cleanly pass the machine verifier
---
# CHECK-LABEL: name: func0
# CHECK: %0:gr32 = PHI undef %1:gr32, %bb.0, undef %1:gr32, %bb.1
name: func0
tracksRegLiveness: true
body: |
bb.0:
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
2019-04-06 03:28:09 +08:00
JCC_1 %bb.1, 4, implicit undef $eflags
MachineVerifier: undef phi arg doesn't need to be live-out from predecessor Differential Revision: https://reviews.llvm.org/D40756 llvm-svn: 319674
2017-12-05 02:57:48 +08:00
JMP_1 %bb.2
bb.1:
bb.2:
%0 : gr32 = PHI undef %1 : gr32, %bb.0, undef %1 : gr32, %bb.1
...
---
# CHECK-LABEL: name: func1
# CHECK: %2:gr32 = PHI %0, %bb.0, %1, %bb.1
name: func1
tracksRegLiveness: true
body: |
bb.0:
%0 : gr32 = IMPLICIT_DEF
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
2019-04-06 03:28:09 +08:00
JCC_1 %bb.1, 4, implicit undef $eflags
MachineVerifier: undef phi arg doesn't need to be live-out from predecessor Differential Revision: https://reviews.llvm.org/D40756 llvm-svn: 319674
2017-12-05 02:57:48 +08:00
JMP_1 %bb.2
bb.1:
%1 : gr32 = IMPLICIT_DEF
bb.2:
%2 : gr32 = PHI %0, %bb.0, %1, %bb.1
...