llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s

---
name: merge_s32_s32_s64_s
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: merge_s32_s32_s64_s
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 0
    ; CHECK: [[EXTRACT1:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 32
    ; CHECK: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
    ; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
    %0:_(s64) = COPY $sgpr0_sgpr1
    %1:_(s32) = G_EXTRACT %0, 0
    %2:_(s32) = G_EXTRACT %0, 32
    %3:_(s64) = G_MERGE_VALUES %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: merge_s32_s32_s64_v
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: merge_s32_s32_s64_v
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 0
    ; CHECK: [[EXTRACT1:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 32
    ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
    ; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_EXTRACT %0, 0
    %2:_(s32) = G_EXTRACT %0, 32
    %3:_(s64) = G_MERGE_VALUES %1, %2
    S_ENDPGM 0, implicit %3
...