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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir

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AMDGPU/GlobalISel: Basic legality for load/store llvm-svn: 327772
2018-03-17 23:17:41 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
GlobalISel: Handle odd splits in fewerElementsVector for load/store llvm-svn: 352720
2019-01-31 10:46:05 +08:00
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
AMDGPU/GlobalISel: Basic legality for load/store llvm-svn: 327772
2018-03-17 23:17:41 +08:00
---
name: test_store_global_i32
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
GlobalISel: Handle odd splits in fewerElementsVector for load/store llvm-svn: 352720
2019-01-31 10:46:05 +08:00
; SI-LABEL: name: test_store_global_i32
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store 4, addrspace 1)
; VI-LABEL: name: test_store_global_i32
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store 4, addrspace 1)
AMDGPU/GlobalISel: Basic legality for load/store llvm-svn: 327772
2018-03-17 23:17:41 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
G_STORE %1, %0 :: (store 4, addrspace 1)
...
---
name: test_store_global_i64
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
GlobalISel: Handle odd splits in fewerElementsVector for load/store llvm-svn: 352720
2019-01-31 10:46:05 +08:00
; SI-LABEL: name: test_store_global_i64
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store 8, addrspace 1)
; VI-LABEL: name: test_store_global_i64
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store 8, addrspace 1)
AMDGPU/GlobalISel: Basic legality for load/store llvm-svn: 327772
2018-03-17 23:17:41 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
G_STORE %1, %0 :: (store 8, addrspace 1)
...
---
name: test_store_global_p1
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
GlobalISel: Handle odd splits in fewerElementsVector for load/store llvm-svn: 352720
2019-01-31 10:46:05 +08:00
; SI-LABEL: name: test_store_global_p1
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr2_vgpr3
; SI: G_STORE [[COPY1]](p1), [[COPY]](p1) :: (store 8, addrspace 1)
; VI-LABEL: name: test_store_global_p1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr2_vgpr3
; VI: G_STORE [[COPY1]](p1), [[COPY]](p1) :: (store 8, addrspace 1)
AMDGPU/GlobalISel: Basic legality for load/store llvm-svn: 327772
2018-03-17 23:17:41 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(p1) = COPY $vgpr2_vgpr3
G_STORE %1, %0 :: (store 8, addrspace 1)
...
---
name: test_store_global_p4
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
GlobalISel: Handle odd splits in fewerElementsVector for load/store llvm-svn: 352720
2019-01-31 10:46:05 +08:00
; SI-LABEL: name: test_store_global_p4
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(p4) = COPY $vgpr2_vgpr3
; SI: G_STORE [[COPY1]](p4), [[COPY]](p1) :: (store 8, addrspace 1)
; VI-LABEL: name: test_store_global_p4
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(p4) = COPY $vgpr2_vgpr3
; VI: G_STORE [[COPY1]](p4), [[COPY]](p1) :: (store 8, addrspace 1)
AMDGPU/GlobalISel: Basic legality for load/store llvm-svn: 327772
2018-03-17 23:17:41 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(p4) = COPY $vgpr2_vgpr3
G_STORE %1, %0 :: (store 8, addrspace 1)
...
---
name: test_store_global_p3
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
GlobalISel: Handle odd splits in fewerElementsVector for load/store llvm-svn: 352720
2019-01-31 10:46:05 +08:00
; SI-LABEL: name: test_store_global_p3
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
; SI: G_STORE [[COPY1]](p3), [[COPY]](p1) :: (store 4, addrspace 1)
; VI-LABEL: name: test_store_global_p3
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
; VI: G_STORE [[COPY1]](p3), [[COPY]](p1) :: (store 4, addrspace 1)
AMDGPU/GlobalISel: Basic legality for load/store llvm-svn: 327772
2018-03-17 23:17:41 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(p3) = COPY $vgpr2
G_STORE %1, %0 :: (store 4, addrspace 1)
...
---
name: test_store_global_v2s32
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
GlobalISel: Handle odd splits in fewerElementsVector for load/store llvm-svn: 352720
2019-01-31 10:46:05 +08:00
; SI-LABEL: name: test_store_global_v2s32
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; SI: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store 8, addrspace 1)
; VI-LABEL: name: test_store_global_v2s32
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; VI: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store 8, addrspace 1)
AMDGPU/GlobalISel: Basic legality for load/store llvm-svn: 327772
2018-03-17 23:17:41 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
G_STORE %1, %0 :: (store 8, addrspace 1)
...
---
name: test_store_global_v2s16
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
GlobalISel: Handle odd splits in fewerElementsVector for load/store llvm-svn: 352720
2019-01-31 10:46:05 +08:00
; SI-LABEL: name: test_store_global_v2s16
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
; SI: G_STORE [[COPY1]](<2 x s16>), [[COPY]](p1) :: (store 4, addrspace 1)
; VI-LABEL: name: test_store_global_v2s16
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
; VI: G_STORE [[COPY1]](<2 x s16>), [[COPY]](p1) :: (store 4, addrspace 1)
AMDGPU/GlobalISel: Basic legality for load/store llvm-svn: 327772
2018-03-17 23:17:41 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = COPY $vgpr2
G_STORE %1, %0 :: (store 4, addrspace 1)
...
---
name: test_store_global_v3s32
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
GlobalISel: Handle odd splits in fewerElementsVector for load/store llvm-svn: 352720
2019-01-31 10:46:05 +08:00
; SI-LABEL: name: test_store_global_v3s32
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; SI: [[EXTRACT:%[0-9]+]]:_(<2 x s32>) = G_EXTRACT [[COPY1]](<3 x s32>), 0
; SI: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](<3 x s32>), 64
; SI: G_STORE [[EXTRACT]](<2 x s32>), [[COPY]](p1) :: (store 8, align 4, addrspace 1)
; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[GEP:%[0-9]+]]:_(p1) = G_GEP [[COPY]], [[C]](s64)
; SI: G_STORE [[EXTRACT1]](s32), [[GEP]](p1) :: (store 4, addrspace 1)
; VI-LABEL: name: test_store_global_v3s32
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; VI: G_STORE [[COPY1]](<3 x s32>), [[COPY]](p1) :: (store 12, align 4, addrspace 1)
AMDGPU/GlobalISel: Basic legality for load/store llvm-svn: 327772
2018-03-17 23:17:41 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
G_STORE %1, %0 :: (store 12, align 4, addrspace 1)
...
GlobalISel: Fix narrowScalar for load/store with different mem size This was ignoring the memory size, and producing multiple loads/stores if the operand size was different from the memory size. I assume this is the intent of not having an explicit G_ANYEXTLOAD (although I think that would probably be better). llvm-svn: 352523
2019-01-30 02:13:02 +08:00
---
name: test_truncstore_global_s64_to_s8
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
GlobalISel: Handle odd splits in fewerElementsVector for load/store llvm-svn: 352720
2019-01-31 10:46:05 +08:00
; SI-LABEL: name: test_truncstore_global_s64_to_s8
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; SI: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store 1, addrspace 1)
; VI-LABEL: name: test_truncstore_global_s64_to_s8
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; VI: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store 1, addrspace 1)
GlobalISel: Fix narrowScalar for load/store with different mem size This was ignoring the memory size, and producing multiple loads/stores if the operand size was different from the memory size. I assume this is the intent of not having an explicit G_ANYEXTLOAD (although I think that would probably be better). llvm-svn: 352523
2019-01-30 02:13:02 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
G_STORE %1, %0 :: (store 1, addrspace 1)
...
---
name: test_truncstore_global_s64_to_s16
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
GlobalISel: Handle odd splits in fewerElementsVector for load/store llvm-svn: 352720
2019-01-31 10:46:05 +08:00
; SI-LABEL: name: test_truncstore_global_s64_to_s16
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; SI: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store 1, addrspace 1)
; VI-LABEL: name: test_truncstore_global_s64_to_s16
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; VI: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store 1, addrspace 1)
GlobalISel: Fix narrowScalar for load/store with different mem size This was ignoring the memory size, and producing multiple loads/stores if the operand size was different from the memory size. I assume this is the intent of not having an explicit G_ANYEXTLOAD (although I think that would probably be better). llvm-svn: 352523
2019-01-30 02:13:02 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
G_STORE %1, %0 :: (store 1, addrspace 1)
...
---
name: test_truncstore_global_s64_to_s32
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
GlobalISel: Handle odd splits in fewerElementsVector for load/store llvm-svn: 352720
2019-01-31 10:46:05 +08:00
; SI-LABEL: name: test_truncstore_global_s64_to_s32
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; SI: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store 4, addrspace 1)
; VI-LABEL: name: test_truncstore_global_s64_to_s32
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; VI: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store 4, addrspace 1)
GlobalISel: Fix narrowScalar for load/store with different mem size This was ignoring the memory size, and producing multiple loads/stores if the operand size was different from the memory size. I assume this is the intent of not having an explicit G_ANYEXTLOAD (although I think that would probably be better). llvm-svn: 352523
2019-01-30 02:13:02 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
G_STORE %1, %0 :: (store 4, addrspace 1)
...
---
name: test_truncstore_global_s128_to_s16
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
GlobalISel: Handle more cases for widenScalar for G_STORE llvm-svn: 352585
2019-01-30 10:04:31 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
G_STORE %1, %0 :: (store 2, addrspace 1)
...
---
name: test_truncstore_global_s128_to_s8
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
GlobalISel: Handle odd splits in fewerElementsVector for load/store llvm-svn: 352720
2019-01-31 10:46:05 +08:00
; SI-LABEL: name: test_truncstore_global_s128_to_s16
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; SI: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store 1, addrspace 1)
; VI-LABEL: name: test_truncstore_global_s128_to_s16
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; VI: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store 1, addrspace 1)
GlobalISel: Fix narrowScalar for load/store with different mem size This was ignoring the memory size, and producing multiple loads/stores if the operand size was different from the memory size. I assume this is the intent of not having an explicit G_ANYEXTLOAD (although I think that would probably be better). llvm-svn: 352523
2019-01-30 02:13:02 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
G_STORE %1, %0 :: (store 1, addrspace 1)
...
GlobalISel: Handle more cases for widenScalar for G_STORE llvm-svn: 352585
2019-01-30 10:04:31 +08:00
name: test_store_global_i1
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s1) = G_TRUNC %1
G_STORE %2, %0 :: (store 1, addrspace 1)
...
---
name: test_store_global_i8
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
GlobalISel: Consolidate load/store legalization The fewerElementsVectors implementation for load/stores handles the scalar reduction case just as well, so drop the redundant code in narrowScalar. This also introduces support for narrowing irregular size breakdowns for scalars. llvm-svn: 353125
2019-02-05 08:26:12 +08:00
; SI-LABEL: name: test_store_global_i8
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store 1, addrspace 1)
; VI-LABEL: name: test_store_global_i8
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store 1, addrspace 1)
GlobalISel: Handle more cases for widenScalar for G_STORE llvm-svn: 352585
2019-01-30 10:04:31 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s8) = G_TRUNC %1
G_STORE %2, %0 :: (store 1, addrspace 1)
...
---
name: test_store_global_i16
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
GlobalISel: Consolidate load/store legalization The fewerElementsVectors implementation for load/stores handles the scalar reduction case just as well, so drop the redundant code in narrowScalar. This also introduces support for narrowing irregular size breakdowns for scalars. llvm-svn: 353125
2019-02-05 08:26:12 +08:00
; SI-LABEL: name: test_store_global_i16
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store 2, addrspace 1)
; VI-LABEL: name: test_store_global_i16
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store 2, addrspace 1)
GlobalISel: Handle more cases for widenScalar for G_STORE llvm-svn: 352585
2019-01-30 10:04:31 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
G_STORE %2, %0 :: (store 2, addrspace 1)
...
GlobalISel: Consolidate load/store legalization The fewerElementsVectors implementation for load/stores handles the scalar reduction case just as well, so drop the redundant code in narrowScalar. This also introduces support for narrowing irregular size breakdowns for scalars. llvm-svn: 353125
2019-02-05 08:26:12 +08:00
---
name: test_store_global_96
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
; SI-LABEL: name: test_store_global_96
; SI: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; SI: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr3_vgpr4
; SI: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s96), 0
; SI: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s96), 64
; SI: G_STORE [[EXTRACT]](s64), [[COPY1]](p1) :: (store 8, align 16, addrspace 1)
; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[GEP:%[0-9]+]]:_(p1) = G_GEP [[COPY1]], [[C]](s64)
; SI: G_STORE [[EXTRACT1]](s32), [[GEP]](p1) :: (store 4, align 8, addrspace 1)
; VI-LABEL: name: test_store_global_96
; VI: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; VI: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr3_vgpr4
; VI: G_STORE [[COPY]](s96), [[COPY1]](p1) :: (store 12, align 16, addrspace 1)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(p1) = COPY $vgpr3_vgpr4
G_STORE %0, %1 :: (store 12, addrspace 1, align 16)
...
GlobalISel: Handle more cases for widenScalar for G_STORE llvm-svn: 352585
2019-01-30 10:04:31 +08:00
---
name: test_store_global_i128
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
GlobalISel: Consolidate load/store legalization The fewerElementsVectors implementation for load/stores handles the scalar reduction case just as well, so drop the redundant code in narrowScalar. This also introduces support for narrowing irregular size breakdowns for scalars. llvm-svn: 353125
2019-02-05 08:26:12 +08:00
; SI-LABEL: name: test_store_global_i128
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI: G_STORE [[COPY1]](s128), [[COPY]](p1) :: (store 16, addrspace 1)
; VI-LABEL: name: test_store_global_i128
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI: G_STORE [[COPY1]](s128), [[COPY]](p1) :: (store 16, addrspace 1)
GlobalISel: Handle more cases for widenScalar for G_STORE llvm-svn: 352585
2019-01-30 10:04:31 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
G_STORE %1, %0 :: (store 16, addrspace 1)
...
---
name: test_store_global_v2s64
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
GlobalISel: Consolidate load/store legalization The fewerElementsVectors implementation for load/stores handles the scalar reduction case just as well, so drop the redundant code in narrowScalar. This also introduces support for narrowing irregular size breakdowns for scalars. llvm-svn: 353125
2019-02-05 08:26:12 +08:00
; SI-LABEL: name: test_store_global_v2s64
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store 16, addrspace 1)
; VI-LABEL: name: test_store_global_v2s64
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store 16, addrspace 1)
GlobalISel: Handle more cases for widenScalar for G_STORE llvm-svn: 352585
2019-01-30 10:04:31 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
G_STORE %1, %0 :: (store 16, addrspace 1)
...