2012-08-01 06:50:19 +08:00
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//===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips32/64 implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSEFrameLowering.h"
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2012-12-04 00:50:05 +08:00
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#include "MCTargetDesc/MipsBaseInfo.h"
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2012-08-01 06:50:19 +08:00
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#include "MipsAnalyzeImmediate.h"
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#include "MipsMachineFunction.h"
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2012-12-04 00:50:05 +08:00
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#include "MipsSEInstrInfo.h"
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2014-07-03 07:29:55 +08:00
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#include "MipsSubtarget.h"
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2015-10-26 20:38:43 +08:00
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#include "llvm/ADT/StringSwitch.h"
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2012-08-01 06:50:19 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2012-11-03 08:05:43 +08:00
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#include "llvm/CodeGen/RegisterScavenging.h"
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2013-01-02 19:36:10 +08:00
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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2012-08-01 06:50:19 +08:00
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#include "llvm/Support/CommandLine.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Target/TargetOptions.h"
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2012-08-01 06:50:19 +08:00
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using namespace llvm;
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2013-03-30 09:04:11 +08:00
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namespace {
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typedef MachineBasicBlock::iterator Iter;
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2013-10-08 02:49:46 +08:00
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static std::pair<unsigned, unsigned> getMFHiLoOpc(unsigned Src) {
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if (Mips::ACC64RegClass.contains(Src))
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return std::make_pair((unsigned)Mips::PseudoMFHI,
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(unsigned)Mips::PseudoMFLO);
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if (Mips::ACC64DSPRegClass.contains(Src))
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return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);
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if (Mips::ACC128RegClass.contains(Src))
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return std::make_pair((unsigned)Mips::PseudoMFHI64,
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(unsigned)Mips::PseudoMFLO64);
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return std::make_pair(0, 0);
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}
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2013-05-02 07:41:31 +08:00
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/// Helper class to expand pseudos.
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class ExpandPseudo {
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2013-03-30 09:04:11 +08:00
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public:
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2013-05-02 07:41:31 +08:00
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ExpandPseudo(MachineFunction &MF);
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2013-03-30 09:04:11 +08:00
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bool expand();
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private:
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bool expandInstr(MachineBasicBlock &MBB, Iter I);
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2013-05-03 07:07:05 +08:00
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void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
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void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
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2013-05-02 07:41:31 +08:00
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void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
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2013-10-08 02:49:46 +08:00
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void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
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unsigned MFLoOpc, unsigned RegSize);
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2013-05-01 07:22:09 +08:00
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bool expandCopy(MachineBasicBlock &MBB, Iter I);
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2013-10-08 02:49:46 +08:00
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bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
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unsigned MFLoOpc);
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2014-07-14 17:40:29 +08:00
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bool expandBuildPairF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, bool FP64) const;
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2014-07-14 21:08:14 +08:00
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bool expandExtractElementF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, bool FP64) const;
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2013-03-30 09:04:11 +08:00
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MachineFunction &MF;
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MachineRegisterInfo &MRI;
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2015-01-30 07:27:36 +08:00
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const MipsSubtarget &Subtarget;
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const MipsSEInstrInfo &TII;
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const MipsRegisterInfo &RegInfo;
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2013-03-30 09:04:11 +08:00
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};
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2015-06-23 17:49:53 +08:00
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}
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2013-03-30 09:04:11 +08:00
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2013-05-02 07:41:31 +08:00
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ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
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2015-01-30 07:27:36 +08:00
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: MF(MF_), MRI(MF.getRegInfo()),
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Subtarget(static_cast<const MipsSubtarget &>(MF.getSubtarget())),
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TII(*static_cast<const MipsSEInstrInfo *>(Subtarget.getInstrInfo())),
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RegInfo(*Subtarget.getRegisterInfo()) {}
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2013-03-30 09:04:11 +08:00
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2013-05-02 07:41:31 +08:00
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bool ExpandPseudo::expand() {
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2013-03-30 09:04:11 +08:00
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bool Expanded = false;
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for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end();
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BB != BBEnd; ++BB)
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for (Iter I = BB->begin(), End = BB->end(); I != End;)
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Expanded |= expandInstr(*BB, I++);
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return Expanded;
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}
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2013-05-02 07:41:31 +08:00
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bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
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2013-03-30 09:04:11 +08:00
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switch(I->getOpcode()) {
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2013-05-03 07:07:05 +08:00
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case Mips::LOAD_CCOND_DSP:
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expandLoadCCond(MBB, I);
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break;
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case Mips::STORE_CCOND_DSP:
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expandStoreCCond(MBB, I);
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break;
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2013-08-09 05:54:26 +08:00
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case Mips::LOAD_ACC64:
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case Mips::LOAD_ACC64DSP:
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2013-05-02 07:41:31 +08:00
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expandLoadACC(MBB, I, 4);
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2013-03-30 09:04:11 +08:00
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break;
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2013-08-09 05:54:26 +08:00
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case Mips::LOAD_ACC128:
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2013-05-02 07:41:31 +08:00
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expandLoadACC(MBB, I, 8);
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2013-03-30 09:04:11 +08:00
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break;
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2013-08-09 05:54:26 +08:00
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case Mips::STORE_ACC64:
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2013-10-08 02:49:46 +08:00
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expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);
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break;
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2013-08-09 05:54:26 +08:00
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case Mips::STORE_ACC64DSP:
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2013-10-08 02:49:46 +08:00
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expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);
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2013-03-30 09:04:11 +08:00
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break;
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2013-08-09 05:54:26 +08:00
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case Mips::STORE_ACC128:
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2013-10-08 02:49:46 +08:00
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expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
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2013-03-30 09:04:11 +08:00
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break;
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2014-07-14 17:40:29 +08:00
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case Mips::BuildPairF64:
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if (expandBuildPairF64(MBB, I, false))
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MBB.erase(I);
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return false;
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case Mips::BuildPairF64_64:
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if (expandBuildPairF64(MBB, I, true))
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MBB.erase(I);
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return false;
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2014-07-14 21:08:14 +08:00
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case Mips::ExtractElementF64:
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if (expandExtractElementF64(MBB, I, false))
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MBB.erase(I);
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return false;
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case Mips::ExtractElementF64_64:
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if (expandExtractElementF64(MBB, I, true))
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MBB.erase(I);
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return false;
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2013-05-01 07:22:09 +08:00
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case TargetOpcode::COPY:
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if (!expandCopy(MBB, I))
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return false;
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2013-03-30 09:04:11 +08:00
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break;
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default:
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return false;
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}
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MBB.erase(I);
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return true;
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}
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2013-05-03 07:07:05 +08:00
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void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
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// load $vr, FI
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// copy ccond, $vr
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const TargetRegisterClass *RC = RegInfo.intRegClass(4);
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unsigned VR = MRI.createVirtualRegister(RC);
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unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
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BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
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.addReg(VR, RegState::Kill);
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}
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void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
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// copy $vr, ccond
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// store $vr, FI
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const TargetRegisterClass *RC = RegInfo.intRegClass(4);
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unsigned VR = MRI.createVirtualRegister(RC);
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unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
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.addReg(Src, getKillRegState(I->getOperand(0).isKill()));
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TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
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}
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2013-05-02 07:41:31 +08:00
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void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
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2013-03-30 09:04:11 +08:00
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unsigned RegSize) {
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// load $vr0, FI
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// copy lo, $vr0
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// load $vr1, FI + 4
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// copy hi, $vr1
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
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unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
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DebugLoc DL = I->getDebugLoc();
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const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
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TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
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BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
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TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
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BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
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}
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2013-05-02 07:41:31 +08:00
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void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
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2013-10-08 02:49:46 +08:00
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unsigned MFHiOpc, unsigned MFLoOpc,
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2013-03-30 09:04:11 +08:00
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unsigned RegSize) {
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2013-10-08 02:49:46 +08:00
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// mflo $vr0, src
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2013-03-30 09:04:11 +08:00
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// store $vr0, FI
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2013-10-08 02:49:46 +08:00
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// mfhi $vr1, src
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2013-03-30 09:04:11 +08:00
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// store $vr1, FI + 4
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
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DebugLoc DL = I->getDebugLoc();
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2013-10-08 02:49:46 +08:00
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BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
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2013-03-30 09:04:11 +08:00
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TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
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2013-10-08 02:49:46 +08:00
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BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
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2013-03-30 09:04:11 +08:00
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TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
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}
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2013-05-02 07:41:31 +08:00
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bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
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2013-10-08 02:49:46 +08:00
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unsigned Src = I->getOperand(1).getReg();
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std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src);
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2013-05-02 07:41:31 +08:00
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2013-10-08 02:49:46 +08:00
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if (!Opcodes.first)
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return false;
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2013-05-02 07:41:31 +08:00
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2013-10-08 02:49:46 +08:00
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return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second);
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2013-05-02 07:41:31 +08:00
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}
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2013-10-08 02:49:46 +08:00
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bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
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unsigned MFHiOpc, unsigned MFLoOpc) {
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// mflo $vr0, src
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2013-03-30 09:04:11 +08:00
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// copy dst_lo, $vr0
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2013-10-08 02:49:46 +08:00
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// mfhi $vr1, src
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2013-03-30 09:04:11 +08:00
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// copy dst_hi, $vr1
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2013-10-08 02:49:46 +08:00
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unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
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unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2;
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const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
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2013-03-30 09:04:11 +08:00
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
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unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
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unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
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DebugLoc DL = I->getDebugLoc();
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2013-10-08 02:49:46 +08:00
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BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
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2013-03-30 09:04:11 +08:00
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BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
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.addReg(VR0, RegState::Kill);
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2013-10-08 02:49:46 +08:00
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BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
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2013-03-30 09:04:11 +08:00
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BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
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.addReg(VR1, RegState::Kill);
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2013-05-01 07:22:09 +08:00
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return true;
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2013-03-30 09:04:11 +08:00
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}
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2014-07-14 17:40:29 +08:00
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/// This method expands the same instruction that MipsSEInstrInfo::
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2014-07-14 21:08:14 +08:00
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/// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is not
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/// available and the case where the ABI is FP64A. It is implemented here
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/// because frame indexes are eliminated before MipsSEInstrInfo::
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/// expandBuildPairF64 is called.
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2014-07-14 17:40:29 +08:00
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bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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bool FP64) const {
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// For fpxx and when mthc1 is not available, use:
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// spill + reload via ldc1
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//
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|
|
// The case where dmtc1 is available doesn't need to be handled here
|
|
|
|
// because it never creates a BuildPairF64 node.
|
2014-07-14 21:08:14 +08:00
|
|
|
//
|
|
|
|
// The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
|
|
|
|
// for odd-numbered double precision values (because the lower 32-bits is
|
|
|
|
// transferred with mtc1 which is redirected to the upper half of the even
|
|
|
|
// register). Unfortunately, we have to make this decision before register
|
|
|
|
// allocation so for now we use a spill/reload sequence for all
|
|
|
|
// double-precision values in regardless of being an odd/even register.
|
|
|
|
if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
|
|
|
|
(FP64 && !Subtarget.useOddSPReg())) {
|
2014-07-14 17:40:29 +08:00
|
|
|
unsigned DstReg = I->getOperand(0).getReg();
|
|
|
|
unsigned LoReg = I->getOperand(1).getReg();
|
|
|
|
unsigned HiReg = I->getOperand(2).getReg();
|
|
|
|
|
|
|
|
// It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
|
2014-07-14 21:08:14 +08:00
|
|
|
// the cases where mthc1 is not available). 64-bit architectures and
|
|
|
|
// MIPS32r2 or later can use FGR64 though.
|
|
|
|
assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
|
|
|
|
!Subtarget.isFP64bit());
|
2014-07-14 17:40:29 +08:00
|
|
|
|
|
|
|
const TargetRegisterClass *RC = &Mips::GPR32RegClass;
|
2014-07-14 21:08:14 +08:00
|
|
|
const TargetRegisterClass *RC2 =
|
|
|
|
FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
|
2014-07-14 17:40:29 +08:00
|
|
|
|
2014-07-14 21:08:14 +08:00
|
|
|
// We re-use the same spill slot each time so that the stack frame doesn't
|
|
|
|
// grow too much in functions with a large number of moves.
|
|
|
|
int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2);
|
2014-10-16 23:41:51 +08:00
|
|
|
if (!Subtarget.isLittle())
|
|
|
|
std::swap(LoReg, HiReg);
|
2015-01-30 07:27:36 +08:00
|
|
|
TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
|
|
|
|
&RegInfo, 0);
|
|
|
|
TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC,
|
|
|
|
&RegInfo, 4);
|
|
|
|
TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, 0);
|
2014-07-14 17:40:29 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-07-14 21:08:14 +08:00
|
|
|
/// This method expands the same instruction that MipsSEInstrInfo::
|
|
|
|
/// expandExtractElementF64 does, for the case when ABI is fpxx and mfhc1 is not
|
|
|
|
/// available and the case where the ABI is FP64A. It is implemented here
|
|
|
|
/// because frame indexes are eliminated before MipsSEInstrInfo::
|
|
|
|
/// expandExtractElementF64 is called.
|
|
|
|
bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I,
|
|
|
|
bool FP64) const {
|
2015-10-12 21:55:44 +08:00
|
|
|
const MachineOperand &Op1 = I->getOperand(1);
|
|
|
|
const MachineOperand &Op2 = I->getOperand(2);
|
|
|
|
|
|
|
|
if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) {
|
|
|
|
unsigned DstReg = I->getOperand(0).getReg();
|
|
|
|
BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2014-07-14 21:08:14 +08:00
|
|
|
// For fpxx and when mfhc1 is not available, use:
|
|
|
|
// spill + reload via ldc1
|
|
|
|
//
|
|
|
|
// The case where dmfc1 is available doesn't need to be handled here
|
|
|
|
// because it never creates a ExtractElementF64 node.
|
|
|
|
//
|
|
|
|
// The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
|
|
|
|
// for odd-numbered double precision values (because the lower 32-bits is
|
|
|
|
// transferred with mfc1 which is redirected to the upper half of the even
|
|
|
|
// register). Unfortunately, we have to make this decision before register
|
|
|
|
// allocation so for now we use a spill/reload sequence for all
|
|
|
|
// double-precision values in regardless of being an odd/even register.
|
|
|
|
|
|
|
|
if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
|
|
|
|
(FP64 && !Subtarget.useOddSPReg())) {
|
|
|
|
unsigned DstReg = I->getOperand(0).getReg();
|
2015-10-12 21:55:44 +08:00
|
|
|
unsigned SrcReg = Op1.getReg();
|
|
|
|
unsigned N = Op2.getImm();
|
2014-10-16 23:41:51 +08:00
|
|
|
int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N));
|
2014-07-14 21:08:14 +08:00
|
|
|
|
|
|
|
// It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
|
|
|
|
// the cases where mfhc1 is not available). 64-bit architectures and
|
|
|
|
// MIPS32r2 or later can use FGR64 though.
|
|
|
|
assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
|
|
|
|
!Subtarget.isFP64bit());
|
|
|
|
|
|
|
|
const TargetRegisterClass *RC =
|
|
|
|
FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
|
|
|
|
const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;
|
|
|
|
|
|
|
|
// We re-use the same spill slot each time so that the stack frame doesn't
|
|
|
|
// grow too much in functions with a large number of moves.
|
|
|
|
int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC);
|
2015-10-12 21:55:44 +08:00
|
|
|
TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0);
|
2015-01-30 07:27:36 +08:00
|
|
|
TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset);
|
2014-07-14 21:08:14 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-07-03 07:29:55 +08:00
|
|
|
MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)
|
|
|
|
: MipsFrameLowering(STI, STI.stackAlignment()) {}
|
|
|
|
|
[ShrinkWrap] Add (a simplified version) of shrink-wrapping.
This patch introduces a new pass that computes the safe point to insert the
prologue and epilogue of the function.
The interest is to find safe points that are cheaper than the entry and exits
blocks.
As an example and to avoid regressions to be introduce, this patch also
implements the required bits to enable the shrink-wrapping pass for AArch64.
** Context **
Currently we insert the prologue and epilogue of the method/function in the
entry and exits blocks. Although this is correct, we can do a better job when
those are not immediately required and insert them at less frequently executed
places.
The job of the shrink-wrapping pass is to identify such places.
** Motivating example **
Let us consider the following function that perform a call only in one branch of
a if:
define i32 @f(i32 %a, i32 %b) {
%tmp = alloca i32, align 4
%tmp2 = icmp slt i32 %a, %b
br i1 %tmp2, label %true, label %false
true:
store i32 %a, i32* %tmp, align 4
%tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
br label %false
false:
%tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
ret i32 %tmp.0
}
On AArch64 this code generates (removing the cfi directives to ease
readabilities):
_f: ; @f
; BB#0:
stp x29, x30, [sp, #-16]!
mov x29, sp
sub sp, sp, #16 ; =16
cmp w0, w1
b.ge LBB0_2
; BB#1: ; %true
stur w0, [x29, #-4]
sub x1, x29, #4 ; =4
mov w0, wzr
bl _doSomething
LBB0_2: ; %false
mov sp, x29
ldp x29, x30, [sp], #16
ret
With shrink-wrapping we could generate:
_f: ; @f
; BB#0:
cmp w0, w1
b.ge LBB0_2
; BB#1: ; %true
stp x29, x30, [sp, #-16]!
mov x29, sp
sub sp, sp, #16 ; =16
stur w0, [x29, #-4]
sub x1, x29, #4 ; =4
mov w0, wzr
bl _doSomething
add sp, x29, #16 ; =16
ldp x29, x30, [sp], #16
LBB0_2: ; %false
ret
Therefore, we would pay the overhead of setting up/destroying the frame only if
we actually do the call.
** Proposed Solution **
This patch introduces a new machine pass that perform the shrink-wrapping
analysis (See the comments at the beginning of ShrinkWrap.cpp for more details).
It then stores the safe save and restore point into the MachineFrameInfo
attached to the MachineFunction.
This information is then used by the PrologEpilogInserter (PEI) to place the
related code at the right place. This pass runs right before the PEI.
Unlike the original paper of Chow from PLDI’88, this implementation of
shrink-wrapping does not use expensive data-flow analysis and does not need hack
to properly avoid frequently executed point. Instead, it relies on dominance and
loop properties.
The pass is off by default and each target can opt-in by setting the
EnableShrinkWrap boolean to true in their derived class of TargetPassConfig.
This setting can also be overwritten on the command line by using
-enable-shrink-wrap.
Before you try out the pass for your target, make sure you properly fix your
emitProlog/emitEpilog/adjustForXXX method to cope with basic blocks that are not
necessarily the entry block.
** Design Decisions **
1. ShrinkWrap is its own pass right now. It could frankly be merged into PEI but
for debugging and clarity I thought it was best to have its own file.
2. Right now, we only support one save point and one restore point. At some
point we can expand this to several save point and restore point, the impacted
component would then be:
- The pass itself: New algorithm needed.
- MachineFrameInfo: Hold a list or set of Save/Restore point instead of one
pointer.
- PEI: Should loop over the save point and restore point.
Anyhow, at least for this first iteration, I do not believe this is interesting
to support the complex cases. We should revisit that when we motivating
examples.
Differential Revision: http://reviews.llvm.org/D9210
<rdar://problem/3201744>
llvm-svn: 236507
2015-05-06 01:38:16 +08:00
|
|
|
void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
|
|
|
|
MachineBasicBlock &MBB) const {
|
|
|
|
assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
|
2012-08-01 06:50:19 +08:00
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2013-01-30 08:26:49 +08:00
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
2013-06-07 15:04:14 +08:00
|
|
|
|
2012-08-01 07:52:55 +08:00
|
|
|
const MipsSEInstrInfo &TII =
|
2015-01-30 07:27:36 +08:00
|
|
|
*static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
|
|
|
|
const MipsRegisterInfo &RegInfo =
|
|
|
|
*static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
|
2013-06-07 15:04:14 +08:00
|
|
|
|
2012-08-01 06:50:19 +08:00
|
|
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
2015-08-29 01:53:26 +08:00
|
|
|
DebugLoc dl;
|
2015-04-17 17:50:21 +08:00
|
|
|
MipsABIInfo ABI = STI.getABI();
|
|
|
|
unsigned SP = ABI.GetStackPtr();
|
|
|
|
unsigned FP = ABI.GetFramePtr();
|
|
|
|
unsigned ZERO = ABI.GetNullPtr();
|
2015-08-11 16:56:25 +08:00
|
|
|
unsigned MOVE = ABI.GetGPRMoveOp();
|
2015-06-02 21:14:46 +08:00
|
|
|
unsigned ADDiu = ABI.GetPtrAddiuOp();
|
|
|
|
unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND;
|
|
|
|
|
|
|
|
const TargetRegisterClass *RC = ABI.ArePtrs64bit() ?
|
|
|
|
&Mips::GPR64RegClass : &Mips::GPR32RegClass;
|
2012-08-01 06:50:19 +08:00
|
|
|
|
|
|
|
// First, compute final stack size.
|
|
|
|
uint64_t StackSize = MFI->getStackSize();
|
|
|
|
|
|
|
|
// No need to allocate space on the stack.
|
|
|
|
if (StackSize == 0 && !MFI->adjustsStack()) return;
|
|
|
|
|
|
|
|
MachineModuleInfo &MMI = MF.getMMI();
|
2013-06-18 15:20:20 +08:00
|
|
|
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
|
2012-08-01 06:50:19 +08:00
|
|
|
MachineLocation DstML, SrcML;
|
|
|
|
|
|
|
|
// Adjust stack.
|
2012-08-01 07:52:55 +08:00
|
|
|
TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
|
2012-08-01 06:50:19 +08:00
|
|
|
|
|
|
|
// emit ".cfi_def_cfa_offset StackSize"
|
2014-03-07 14:08:31 +08:00
|
|
|
unsigned CFIIndex = MMI.addFrameInst(
|
|
|
|
MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
|
|
|
|
.addCFIIndex(CFIIndex);
|
2012-08-01 06:50:19 +08:00
|
|
|
|
2015-10-26 20:38:43 +08:00
|
|
|
if (MF.getFunction()->hasFnAttribute("interrupt"))
|
|
|
|
emitInterruptPrologueStub(MF, MBB);
|
|
|
|
|
2012-08-01 06:50:19 +08:00
|
|
|
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
|
|
|
|
|
|
|
|
if (CSI.size()) {
|
|
|
|
// Find the instruction past the last instruction that saves a callee-saved
|
|
|
|
// register to the stack.
|
|
|
|
for (unsigned i = 0; i < CSI.size(); ++i)
|
|
|
|
++MBBI;
|
|
|
|
|
|
|
|
// Iterate over list of callee-saved registers and emit .cfi_offset
|
|
|
|
// directives.
|
|
|
|
for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
|
|
|
|
E = CSI.end(); I != E; ++I) {
|
|
|
|
int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
|
|
|
|
unsigned Reg = I->getReg();
|
|
|
|
|
|
|
|
// If Reg is a double precision register, emit two cfa_offsets,
|
|
|
|
// one for each of the paired single precision registers.
|
|
|
|
if (Mips::AFGR64RegClass.contains(Reg)) {
|
2013-05-17 05:02:15 +08:00
|
|
|
unsigned Reg0 =
|
2013-08-21 06:58:56 +08:00
|
|
|
MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
|
2013-05-17 05:02:15 +08:00
|
|
|
unsigned Reg1 =
|
2013-08-21 06:58:56 +08:00
|
|
|
MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
|
2012-08-01 06:50:19 +08:00
|
|
|
|
|
|
|
if (!STI.isLittle())
|
2013-05-17 05:02:15 +08:00
|
|
|
std::swap(Reg0, Reg1);
|
2012-08-01 06:50:19 +08:00
|
|
|
|
2014-03-07 14:08:31 +08:00
|
|
|
unsigned CFIIndex = MMI.addFrameInst(
|
|
|
|
MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
|
|
|
|
.addCFIIndex(CFIIndex);
|
|
|
|
|
|
|
|
CFIIndex = MMI.addFrameInst(
|
|
|
|
MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
|
|
|
|
.addCFIIndex(CFIIndex);
|
2014-07-11 06:23:30 +08:00
|
|
|
} else if (Mips::FGR64RegClass.contains(Reg)) {
|
|
|
|
unsigned Reg0 = MRI->getDwarfRegNum(Reg, true);
|
|
|
|
unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1;
|
|
|
|
|
|
|
|
if (!STI.isLittle())
|
|
|
|
std::swap(Reg0, Reg1);
|
|
|
|
|
|
|
|
unsigned CFIIndex = MMI.addFrameInst(
|
|
|
|
MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
|
|
|
|
.addCFIIndex(CFIIndex);
|
|
|
|
|
|
|
|
CFIIndex = MMI.addFrameInst(
|
|
|
|
MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
|
|
|
|
.addCFIIndex(CFIIndex);
|
2012-08-01 06:50:19 +08:00
|
|
|
} else {
|
2013-08-07 07:08:38 +08:00
|
|
|
// Reg is either in GPR32 or FGR32.
|
2014-03-07 14:08:31 +08:00
|
|
|
unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
|
|
|
|
nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
|
|
|
|
.addCFIIndex(CFIIndex);
|
2012-08-01 06:50:19 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-01-30 08:26:49 +08:00
|
|
|
if (MipsFI->callsEhReturn()) {
|
|
|
|
// Insert instructions that spill eh data registers.
|
|
|
|
for (int I = 0; I < 4; ++I) {
|
2015-04-17 17:50:21 +08:00
|
|
|
if (!MBB.isLiveIn(ABI.GetEhDataReg(I)))
|
|
|
|
MBB.addLiveIn(ABI.GetEhDataReg(I));
|
|
|
|
TII.storeRegToStackSlot(MBB, MBBI, ABI.GetEhDataReg(I), false,
|
2015-06-02 21:14:46 +08:00
|
|
|
MipsFI->getEhDataRegFI(I), RC, &RegInfo);
|
2013-01-30 08:26:49 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Emit .cfi_offset directives for eh data registers.
|
|
|
|
for (int I = 0; I < 4; ++I) {
|
|
|
|
int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
|
2015-04-17 17:50:21 +08:00
|
|
|
unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true);
|
2014-03-07 14:08:31 +08:00
|
|
|
unsigned CFIIndex = MMI.addFrameInst(
|
|
|
|
MCCFIInstruction::createOffset(nullptr, Reg, Offset));
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
|
|
|
|
.addCFIIndex(CFIIndex);
|
2013-01-30 08:26:49 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-08-01 06:50:19 +08:00
|
|
|
// if framepointer enabled, set it to point to the stack pointer.
|
|
|
|
if (hasFP(MF)) {
|
|
|
|
// Insert instruction "move $fp, $sp" at this location.
|
2015-08-11 16:56:25 +08:00
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO)
|
2014-04-15 06:21:22 +08:00
|
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
2012-08-01 06:50:19 +08:00
|
|
|
|
|
|
|
// emit ".cfi_def_cfa_register $fp"
|
2014-03-07 14:08:31 +08:00
|
|
|
unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
|
|
|
|
nullptr, MRI->getDwarfRegNum(FP, true)));
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
|
|
|
|
.addCFIIndex(CFIIndex);
|
2015-06-02 21:14:46 +08:00
|
|
|
|
|
|
|
if (RegInfo.needsStackRealignment(MF)) {
|
|
|
|
// addiu $Reg, $zero, -MaxAlignment
|
|
|
|
// andi $sp, $sp, $Reg
|
|
|
|
unsigned VR = MF.getRegInfo().createVirtualRegister(RC);
|
|
|
|
assert(isInt<16>(MFI->getMaxAlignment()) &&
|
|
|
|
"Function's alignment size requirement is not supported.");
|
|
|
|
int MaxAlign = - (signed) MFI->getMaxAlignment();
|
|
|
|
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);
|
|
|
|
|
|
|
|
if (hasBP(MF)) {
|
|
|
|
// move $s7, $sp
|
|
|
|
unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7;
|
2015-08-11 16:56:25 +08:00
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(MOVE), BP)
|
2015-06-02 21:14:46 +08:00
|
|
|
.addReg(SP)
|
|
|
|
.addReg(ZERO);
|
|
|
|
}
|
|
|
|
}
|
2012-08-01 06:50:19 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-10-26 20:38:43 +08:00
|
|
|
void MipsSEFrameLowering::emitInterruptPrologueStub(
|
|
|
|
MachineFunction &MF, MachineBasicBlock &MBB) const {
|
|
|
|
|
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
|
|
|
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
|
|
|
|
|
|
|
// Report an error the target doesn't support Mips32r2 or later.
|
|
|
|
// The epilogue relies on the use of the "ehb" to clear execution
|
|
|
|
// hazards. Pre R2 Mips relies on an implementation defined number
|
|
|
|
// of "ssnop"s to clear the execution hazard. Support for ssnop hazard
|
|
|
|
// clearing is not provided so reject that configuration.
|
|
|
|
if (!STI.hasMips32r2())
|
|
|
|
report_fatal_error(
|
|
|
|
"\"interrupt\" attribute is not supported on pre-r2 MIPS or"
|
|
|
|
"Mips16 targets.");
|
|
|
|
|
|
|
|
// The GP register contains the "user" value, so we cannot perform
|
|
|
|
// any gp relative loads until we restore the "kernel" or "system" gp
|
|
|
|
// value. Until support is written we shall only accept the static
|
|
|
|
// relocation model.
|
|
|
|
if ((STI.getRelocationModel() != Reloc::Static))
|
|
|
|
report_fatal_error("\"interrupt\" attribute is only supported for the "
|
|
|
|
"static relocation model on MIPS at the present time.");
|
|
|
|
|
|
|
|
if (!STI.isABI_O32() || STI.hasMips64())
|
|
|
|
report_fatal_error("\"interrupt\" attribute is only supported for the "
|
|
|
|
"O32 ABI on MIPS32r2+ at the present time.");
|
|
|
|
|
|
|
|
// Perform ISR handling like GCC
|
|
|
|
StringRef IntKind =
|
|
|
|
MF.getFunction()->getFnAttribute("interrupt").getValueAsString();
|
|
|
|
const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
|
|
|
|
|
|
|
|
// EIC interrupt handling needs to read the Cause register to disable
|
|
|
|
// interrupts.
|
|
|
|
if (IntKind == "eic") {
|
|
|
|
// Coprocessor registers are always live per se.
|
|
|
|
MBB.addLiveIn(Mips::COP013);
|
|
|
|
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0)
|
|
|
|
.addReg(Mips::COP013)
|
|
|
|
.addImm(0)
|
|
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
|
|
|
|
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0)
|
|
|
|
.addReg(Mips::K0)
|
|
|
|
.addImm(10)
|
|
|
|
.addImm(6)
|
|
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Fetch and spill EPC
|
|
|
|
MBB.addLiveIn(Mips::COP014);
|
|
|
|
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
|
|
|
|
.addReg(Mips::COP014)
|
|
|
|
.addImm(0)
|
|
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
|
|
|
|
STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
|
|
|
|
MipsFI->getISRRegFI(0), PtrRC,
|
|
|
|
STI.getRegisterInfo(), 0);
|
|
|
|
|
|
|
|
// Fetch and Spill Status
|
|
|
|
MBB.addLiveIn(Mips::COP012);
|
|
|
|
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
|
|
|
|
.addReg(Mips::COP012)
|
|
|
|
.addImm(0)
|
|
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
|
|
|
|
STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
|
|
|
|
MipsFI->getISRRegFI(1), PtrRC,
|
|
|
|
STI.getRegisterInfo(), 0);
|
|
|
|
|
|
|
|
// Build the configuration for disabling lower priority interrupts. Non EIC
|
|
|
|
// interrupts need to be masked off with zero, EIC from the Cause register.
|
|
|
|
unsigned InsPosition = 8;
|
|
|
|
unsigned InsSize = 0;
|
|
|
|
unsigned SrcReg = Mips::ZERO;
|
|
|
|
|
|
|
|
// If the interrupt we're tied to is the EIC, switch the source for the
|
|
|
|
// masking off interrupts to the cause register.
|
|
|
|
if (IntKind == "eic") {
|
|
|
|
SrcReg = Mips::K0;
|
|
|
|
InsPosition = 10;
|
|
|
|
InsSize = 6;
|
|
|
|
} else
|
|
|
|
InsSize = StringSwitch<unsigned>(IntKind)
|
|
|
|
.Case("sw0", 1)
|
|
|
|
.Case("sw1", 2)
|
|
|
|
.Case("hw0", 3)
|
|
|
|
.Case("hw1", 4)
|
|
|
|
.Case("hw2", 5)
|
|
|
|
.Case("hw3", 6)
|
|
|
|
.Case("hw4", 7)
|
|
|
|
.Case("hw5", 8)
|
|
|
|
.Default(0);
|
|
|
|
assert(InsSize != 0 && "Unknown interrupt type!");
|
|
|
|
|
|
|
|
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
|
|
|
|
.addReg(SrcReg)
|
|
|
|
.addImm(InsPosition)
|
|
|
|
.addImm(InsSize)
|
|
|
|
.addReg(Mips::K1)
|
|
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
|
|
|
|
// Mask off KSU, ERL, EXL
|
|
|
|
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
|
|
|
|
.addReg(Mips::ZERO)
|
|
|
|
.addImm(1)
|
|
|
|
.addImm(4)
|
|
|
|
.addReg(Mips::K1)
|
|
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
|
|
|
|
// Disable the FPU as we are not spilling those register sets.
|
|
|
|
if (!STI.useSoftFloat())
|
|
|
|
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
|
|
|
|
.addReg(Mips::ZERO)
|
|
|
|
.addImm(29)
|
|
|
|
.addImm(1)
|
|
|
|
.addReg(Mips::K1)
|
|
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
|
|
|
|
// Set the new status
|
|
|
|
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
|
|
|
|
.addReg(Mips::K1)
|
|
|
|
.addImm(0)
|
|
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
}
|
|
|
|
|
2012-08-01 06:50:19 +08:00
|
|
|
void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
|
|
|
|
MachineBasicBlock &MBB) const {
|
|
|
|
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2013-01-30 08:26:49 +08:00
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
2013-06-07 15:04:14 +08:00
|
|
|
|
2012-08-01 07:52:55 +08:00
|
|
|
const MipsSEInstrInfo &TII =
|
2015-01-30 07:27:36 +08:00
|
|
|
*static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
|
|
|
|
const MipsRegisterInfo &RegInfo =
|
|
|
|
*static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
|
2013-06-07 15:04:14 +08:00
|
|
|
|
2015-10-26 20:38:43 +08:00
|
|
|
DebugLoc DL = MBBI->getDebugLoc();
|
2015-04-17 17:50:21 +08:00
|
|
|
MipsABIInfo ABI = STI.getABI();
|
|
|
|
unsigned SP = ABI.GetStackPtr();
|
|
|
|
unsigned FP = ABI.GetFramePtr();
|
|
|
|
unsigned ZERO = ABI.GetNullPtr();
|
2015-08-11 16:56:25 +08:00
|
|
|
unsigned MOVE = ABI.GetGPRMoveOp();
|
2012-08-01 06:50:19 +08:00
|
|
|
|
|
|
|
// if framepointer enabled, restore the stack pointer.
|
|
|
|
if (hasFP(MF)) {
|
|
|
|
// Find the first instruction that restores a callee-saved register.
|
|
|
|
MachineBasicBlock::iterator I = MBBI;
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
|
|
|
|
--I;
|
|
|
|
|
|
|
|
// Insert instruction "move $sp, $fp" at this location.
|
2015-10-26 20:38:43 +08:00
|
|
|
BuildMI(MBB, I, DL, TII.get(MOVE), SP).addReg(FP).addReg(ZERO);
|
2012-08-01 06:50:19 +08:00
|
|
|
}
|
|
|
|
|
2013-01-30 08:26:49 +08:00
|
|
|
if (MipsFI->callsEhReturn()) {
|
2015-04-17 17:50:21 +08:00
|
|
|
const TargetRegisterClass *RC =
|
|
|
|
ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
|
2013-01-30 08:26:49 +08:00
|
|
|
|
|
|
|
// Find first instruction that restores a callee-saved register.
|
|
|
|
MachineBasicBlock::iterator I = MBBI;
|
|
|
|
for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
|
|
|
|
--I;
|
|
|
|
|
|
|
|
// Insert instructions that restore eh data registers.
|
|
|
|
for (int J = 0; J < 4; ++J) {
|
2015-04-17 17:50:21 +08:00
|
|
|
TII.loadRegFromStackSlot(MBB, I, ABI.GetEhDataReg(J),
|
|
|
|
MipsFI->getEhDataRegFI(J), RC, &RegInfo);
|
2013-01-30 08:26:49 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-10-26 20:38:43 +08:00
|
|
|
if (MF.getFunction()->hasFnAttribute("interrupt"))
|
|
|
|
emitInterruptEpilogueStub(MF, MBB);
|
|
|
|
|
2012-08-01 06:50:19 +08:00
|
|
|
// Get the number of bytes from FrameInfo
|
|
|
|
uint64_t StackSize = MFI->getStackSize();
|
|
|
|
|
|
|
|
if (!StackSize)
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Adjust stack.
|
2012-08-01 07:52:55 +08:00
|
|
|
TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
|
2012-08-01 06:50:19 +08:00
|
|
|
}
|
|
|
|
|
2015-10-26 20:38:43 +08:00
|
|
|
void MipsSEFrameLowering::emitInterruptEpilogueStub(
|
|
|
|
MachineFunction &MF, MachineBasicBlock &MBB) const {
|
|
|
|
|
|
|
|
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
|
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
|
|
|
|
|
|
|
// Perform ISR handling like GCC
|
|
|
|
const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
|
|
|
|
|
|
|
|
// Disable Interrupts.
|
|
|
|
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO);
|
|
|
|
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB));
|
|
|
|
|
|
|
|
// Restore EPC
|
|
|
|
STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
|
|
|
|
MipsFI->getISRRegFI(0), PtrRC,
|
|
|
|
STI.getRegisterInfo());
|
|
|
|
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014)
|
|
|
|
.addReg(Mips::K1)
|
|
|
|
.addImm(0);
|
|
|
|
|
|
|
|
// Restore Status
|
|
|
|
STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
|
|
|
|
MipsFI->getISRRegFI(1), PtrRC,
|
|
|
|
STI.getRegisterInfo());
|
|
|
|
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
|
|
|
|
.addReg(Mips::K1)
|
|
|
|
.addImm(0);
|
|
|
|
}
|
|
|
|
|
2012-08-01 06:50:19 +08:00
|
|
|
bool MipsSEFrameLowering::
|
|
|
|
spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MI,
|
|
|
|
const std::vector<CalleeSavedInfo> &CSI,
|
|
|
|
const TargetRegisterInfo *TRI) const {
|
|
|
|
MachineFunction *MF = MBB.getParent();
|
2015-10-20 08:15:20 +08:00
|
|
|
MachineBasicBlock *EntryBlock = &MF->front();
|
2015-01-30 07:27:36 +08:00
|
|
|
const TargetInstrInfo &TII = *STI.getInstrInfo();
|
2012-08-01 06:50:19 +08:00
|
|
|
|
|
|
|
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
|
|
|
// Add the callee-saved register as live-in. Do not add if the register is
|
|
|
|
// RA and return address is taken, because it has already been added in
|
|
|
|
// method MipsTargetLowering::LowerRETURNADDR.
|
|
|
|
// It's killed at the spill, unless the register is RA and return address
|
|
|
|
// is taken.
|
|
|
|
unsigned Reg = CSI[i].getReg();
|
|
|
|
bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
|
|
|
|
&& MF->getFrameInfo()->isReturnAddressTaken();
|
|
|
|
if (!IsRAAndRetAddrIsTaken)
|
|
|
|
EntryBlock->addLiveIn(Reg);
|
|
|
|
|
2015-10-26 20:38:43 +08:00
|
|
|
// ISRs require HI/LO to be spilled into kernel registers to be then
|
|
|
|
// spilled to the stack frame.
|
|
|
|
bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 ||
|
|
|
|
Reg == Mips::HI0 || Reg == Mips::HI0_64);
|
|
|
|
const Function *Func = MBB.getParent()->getFunction();
|
|
|
|
if (IsLOHI && Func->hasFnAttribute("interrupt")) {
|
|
|
|
DebugLoc DL = MI->getDebugLoc();
|
|
|
|
|
|
|
|
unsigned Op = 0;
|
|
|
|
if (!STI.getABI().ArePtrs64bit()) {
|
|
|
|
Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO;
|
|
|
|
Reg = Mips::K0;
|
|
|
|
} else {
|
|
|
|
Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64;
|
|
|
|
Reg = Mips::K0_64;
|
|
|
|
}
|
|
|
|
BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0)
|
|
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
}
|
|
|
|
|
2012-08-01 06:50:19 +08:00
|
|
|
// Insert the spill to the stack frame.
|
|
|
|
bool IsKill = !IsRAAndRetAddrIsTaken;
|
|
|
|
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
|
|
|
|
TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
|
|
|
|
CSI[i].getFrameIdx(), RC, TRI);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
|
|
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
|
|
|
|
// Reserve call frame if the size of the maximum call frame fits into 16-bit
|
|
|
|
// immediate field and there are no variable sized objects on the stack.
|
2013-03-30 09:04:11 +08:00
|
|
|
// Make sure the second register scavenger spill slot can be accessed with one
|
|
|
|
// instruction.
|
|
|
|
return isInt<16>(MFI->getMaxCallFrameSize() + getStackAlignment()) &&
|
|
|
|
!MFI->hasVarSizedObjects();
|
2012-08-01 06:50:19 +08:00
|
|
|
}
|
|
|
|
|
2015-07-15 01:17:13 +08:00
|
|
|
/// Mark \p Reg and all registers aliasing it in the bitset.
|
2015-07-16 19:12:05 +08:00
|
|
|
static void setAliasRegs(MachineFunction &MF, BitVector &SavedRegs,
|
|
|
|
unsigned Reg) {
|
2015-07-15 01:17:13 +08:00
|
|
|
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
|
|
|
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
|
|
|
|
SavedRegs.set(*AI);
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF,
|
|
|
|
BitVector &SavedRegs,
|
|
|
|
RegScavenger *RS) const {
|
|
|
|
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
|
2013-01-30 08:26:49 +08:00
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
2015-04-17 17:50:21 +08:00
|
|
|
MipsABIInfo ABI = STI.getABI();
|
|
|
|
unsigned FP = ABI.GetFramePtr();
|
2015-06-02 21:14:46 +08:00
|
|
|
unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7;
|
2012-08-01 06:50:19 +08:00
|
|
|
|
|
|
|
// Mark $fp as used if function has dedicated frame pointer.
|
|
|
|
if (hasFP(MF))
|
2015-07-15 01:17:13 +08:00
|
|
|
setAliasRegs(MF, SavedRegs, FP);
|
2015-06-02 21:14:46 +08:00
|
|
|
// Mark $s7 as used if function has dedicated base pointer.
|
|
|
|
if (hasBP(MF))
|
2015-07-15 01:17:13 +08:00
|
|
|
setAliasRegs(MF, SavedRegs, BP);
|
2012-11-03 08:05:43 +08:00
|
|
|
|
2013-01-30 08:26:49 +08:00
|
|
|
// Create spill slots for eh data registers if function calls eh_return.
|
|
|
|
if (MipsFI->callsEhReturn())
|
|
|
|
MipsFI->createEhDataRegsFI();
|
|
|
|
|
2015-10-26 20:38:43 +08:00
|
|
|
// Create spill slots for Coprocessor 0 registers if function is an ISR.
|
|
|
|
if (MipsFI->isISR())
|
|
|
|
MipsFI->createISRRegFI();
|
|
|
|
|
2013-03-30 09:04:11 +08:00
|
|
|
// Expand pseudo instructions which load, store or copy accumulators.
|
|
|
|
// Add an emergency spill slot if a pseudo was expanded.
|
2013-05-02 07:41:31 +08:00
|
|
|
if (ExpandPseudo(MF).expand()) {
|
2013-03-30 09:04:11 +08:00
|
|
|
// The spill slot should be half the size of the accumulator. If target is
|
|
|
|
// mips64, it should be 64-bit, otherwise it should be 32-bt.
|
|
|
|
const TargetRegisterClass *RC = STI.hasMips64() ?
|
2013-08-07 07:08:38 +08:00
|
|
|
&Mips::GPR64RegClass : &Mips::GPR32RegClass;
|
2013-03-30 09:04:11 +08:00
|
|
|
int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
|
|
|
|
RC->getAlignment(), false);
|
|
|
|
RS->addScavengingFrameIndex(FI);
|
|
|
|
}
|
|
|
|
|
2012-11-03 08:05:43 +08:00
|
|
|
// Set scavenging frame index if necessary.
|
|
|
|
uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
|
|
|
|
estimateStackSize(MF);
|
|
|
|
|
|
|
|
if (isInt<16>(MaxSPOffset))
|
|
|
|
return;
|
|
|
|
|
2015-04-17 17:50:21 +08:00
|
|
|
const TargetRegisterClass *RC =
|
|
|
|
ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
|
2012-11-03 08:05:43 +08:00
|
|
|
int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
|
|
|
|
RC->getAlignment(), false);
|
2013-03-23 07:32:27 +08:00
|
|
|
RS->addScavengingFrameIndex(FI);
|
2012-08-01 06:50:19 +08:00
|
|
|
}
|
2012-08-03 02:21:47 +08:00
|
|
|
|
|
|
|
const MipsFrameLowering *
|
|
|
|
llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
|
|
|
|
return new MipsSEFrameLowering(ST);
|
|
|
|
}
|