maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/X86/extract-store.ll

413 lines
12 KiB
LLVM
Raw Normal View History

[X86][SSE] Regenerate extraction+store memop tests Added tests for SSE2 as well as SSE41+AVX llvm-svn: 275876
2016-07-19 02:44:01 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86][SSE] Add more thorough extract to store tests Added v4i32 and v2i64 tests and test on i686 as well as x86_64. llvm-svn: 294946
2017-02-13 21:40:12 +08:00
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32 --check-prefix=SSE-X32 --check-prefix=SSE2-X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64 --check-prefix=SSE-X64 --check-prefix=SSE2-X64
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X32 --check-prefix=SSE-X32 --check-prefix=SSE41-X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X64 --check-prefix=SSE-X64 --check-prefix=SSE41-X64
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32 --check-prefix=AVX-X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 --check-prefix=AVX-X64
X86: Resolve a long standing FIXME and properly isel pextr[bw]. Generalize the AArch64 .td nodes for AssertZext and AssertSext. Use them to match the relevant pextr store instructions. The test widen_load-2.ll requires a slight change because with the stores gone, the remaining instructions are scheduled in a different order. Add test cases for SSE4 and AVX variants. Resolves rdar://13414672. Patch by Adam Nemet <anemet@apple.com>. llvm-svn: 200957
2014-02-07 08:16:33 +08:00
[X86][SSE] Add more thorough extract to store tests Added v4i32 and v2i64 tests and test on i686 as well as x86_64. llvm-svn: 294946
2017-02-13 21:40:12 +08:00
define void @extract_i8_0(i8* nocapture %dst, <16 x i8> %foo) nounwind {
; SSE2-X32-LABEL: extract_i8_0:
; SSE2-X32: # BB#0:
; SSE2-X32-NEXT: pushl %ebp
; SSE2-X32-NEXT: movl %esp, %ebp
; SSE2-X32-NEXT: andl $-16, %esp
; SSE2-X32-NEXT: subl $32, %esp
; SSE2-X32-NEXT: movl 8(%ebp), %eax
; SSE2-X32-NEXT: movaps %xmm0, (%esp)
; SSE2-X32-NEXT: movb (%esp), %cl
; SSE2-X32-NEXT: movb %cl, (%eax)
; SSE2-X32-NEXT: movl %ebp, %esp
; SSE2-X32-NEXT: popl %ebp
; SSE2-X32-NEXT: retl
;
; SSE2-X64-LABEL: extract_i8_0:
; SSE2-X64: # BB#0:
; SSE2-X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-X64-NEXT: movb -{{[0-9]+}}(%rsp), %al
; SSE2-X64-NEXT: movb %al, (%rdi)
; SSE2-X64-NEXT: retq
;
; SSE41-X32-LABEL: extract_i8_0:
; SSE41-X32: # BB#0:
; SSE41-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE41-X32-NEXT: pextrb $0, %xmm0, (%eax)
; SSE41-X32-NEXT: retl
;
; SSE41-X64-LABEL: extract_i8_0:
; SSE41-X64: # BB#0:
; SSE41-X64-NEXT: pextrb $0, %xmm0, (%rdi)
; SSE41-X64-NEXT: retq
;
; AVX-X32-LABEL: extract_i8_0:
; AVX-X32: # BB#0:
; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; AVX-X32-NEXT: vpextrb $0, %xmm0, (%eax)
; AVX-X32-NEXT: retl
;
; AVX-X64-LABEL: extract_i8_0:
; AVX-X64: # BB#0:
; AVX-X64-NEXT: vpextrb $0, %xmm0, (%rdi)
; AVX-X64-NEXT: retq
[X86][SSE] Regenerate extraction+store memop tests Added tests for SSE2 as well as SSE41+AVX llvm-svn: 275876
2016-07-19 02:44:01 +08:00
%vecext = extractelement <16 x i8> %foo, i32 0
store i8 %vecext, i8* %dst, align 1
ret void
}
[X86][SSE] Add more thorough extract to store tests Added v4i32 and v2i64 tests and test on i686 as well as x86_64. llvm-svn: 294946
2017-02-13 21:40:12 +08:00
define void @extract_i8_3(i8* nocapture %dst, <16 x i8> %foo) nounwind {
; SSE2-X32-LABEL: extract_i8_3:
; SSE2-X32: # BB#0:
; SSE2-X32-NEXT: pushl %ebp
; SSE2-X32-NEXT: movl %esp, %ebp
; SSE2-X32-NEXT: andl $-16, %esp
; SSE2-X32-NEXT: subl $32, %esp
; SSE2-X32-NEXT: movl 8(%ebp), %eax
; SSE2-X32-NEXT: movaps %xmm0, (%esp)
; SSE2-X32-NEXT: movb {{[0-9]+}}(%esp), %cl
; SSE2-X32-NEXT: movb %cl, (%eax)
; SSE2-X32-NEXT: movl %ebp, %esp
; SSE2-X32-NEXT: popl %ebp
; SSE2-X32-NEXT: retl
;
; SSE2-X64-LABEL: extract_i8_3:
; SSE2-X64: # BB#0:
; SSE2-X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-X64-NEXT: movb -{{[0-9]+}}(%rsp), %al
; SSE2-X64-NEXT: movb %al, (%rdi)
; SSE2-X64-NEXT: retq
;
; SSE41-X32-LABEL: extract_i8_3:
; SSE41-X32: # BB#0:
; SSE41-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE41-X32-NEXT: pextrb $3, %xmm0, (%eax)
; SSE41-X32-NEXT: retl
;
; SSE41-X64-LABEL: extract_i8_3:
; SSE41-X64: # BB#0:
; SSE41-X64-NEXT: pextrb $3, %xmm0, (%rdi)
; SSE41-X64-NEXT: retq
;
; AVX-X32-LABEL: extract_i8_3:
; AVX-X32: # BB#0:
; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; AVX-X32-NEXT: vpextrb $3, %xmm0, (%eax)
; AVX-X32-NEXT: retl
;
; AVX-X64-LABEL: extract_i8_3:
; AVX-X64: # BB#0:
; AVX-X64-NEXT: vpextrb $3, %xmm0, (%rdi)
; AVX-X64-NEXT: retq
%vecext = extractelement <16 x i8> %foo, i32 3
store i8 %vecext, i8* %dst, align 1
ret void
}
define void @extract_i8_15(i8* nocapture %dst, <16 x i8> %foo) nounwind {
; SSE2-X32-LABEL: extract_i8_15:
; SSE2-X32: # BB#0:
; SSE2-X32-NEXT: pushl %ebp
; SSE2-X32-NEXT: movl %esp, %ebp
; SSE2-X32-NEXT: andl $-16, %esp
; SSE2-X32-NEXT: subl $32, %esp
; SSE2-X32-NEXT: movl 8(%ebp), %eax
; SSE2-X32-NEXT: movaps %xmm0, (%esp)
; SSE2-X32-NEXT: movb {{[0-9]+}}(%esp), %cl
; SSE2-X32-NEXT: movb %cl, (%eax)
; SSE2-X32-NEXT: movl %ebp, %esp
; SSE2-X32-NEXT: popl %ebp
; SSE2-X32-NEXT: retl
;
; SSE2-X64-LABEL: extract_i8_15:
; SSE2-X64: # BB#0:
; SSE2-X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-X64-NEXT: movb -{{[0-9]+}}(%rsp), %al
; SSE2-X64-NEXT: movb %al, (%rdi)
; SSE2-X64-NEXT: retq
;
; SSE41-X32-LABEL: extract_i8_15:
; SSE41-X32: # BB#0:
; SSE41-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE41-X32-NEXT: pextrb $15, %xmm0, (%eax)
; SSE41-X32-NEXT: retl
;
; SSE41-X64-LABEL: extract_i8_15:
; SSE41-X64: # BB#0:
; SSE41-X64-NEXT: pextrb $15, %xmm0, (%rdi)
; SSE41-X64-NEXT: retq
;
; AVX-X32-LABEL: extract_i8_15:
; AVX-X32: # BB#0:
; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; AVX-X32-NEXT: vpextrb $15, %xmm0, (%eax)
; AVX-X32-NEXT: retl
;
; AVX-X64-LABEL: extract_i8_15:
; AVX-X64: # BB#0:
; AVX-X64-NEXT: vpextrb $15, %xmm0, (%rdi)
; AVX-X64-NEXT: retq
X86: Resolve a long standing FIXME and properly isel pextr[bw]. Generalize the AArch64 .td nodes for AssertZext and AssertSext. Use them to match the relevant pextr store instructions. The test widen_load-2.ll requires a slight change because with the stores gone, the remaining instructions are scheduled in a different order. Add test cases for SSE4 and AVX variants. Resolves rdar://13414672. Patch by Adam Nemet <anemet@apple.com>. llvm-svn: 200957
2014-02-07 08:16:33 +08:00
%vecext = extractelement <16 x i8> %foo, i32 15
store i8 %vecext, i8* %dst, align 1
ret void
}
[X86][SSE] Add more thorough extract to store tests Added v4i32 and v2i64 tests and test on i686 as well as x86_64. llvm-svn: 294946
2017-02-13 21:40:12 +08:00
define void @extract_i16_0(i16* nocapture %dst, <8 x i16> %foo) nounwind {
; SSE2-X32-LABEL: extract_i16_0:
; SSE2-X32: # BB#0:
; SSE2-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE2-X32-NEXT: movd %xmm0, %ecx
; SSE2-X32-NEXT: movw %cx, (%eax)
; SSE2-X32-NEXT: retl
;
; SSE2-X64-LABEL: extract_i16_0:
; SSE2-X64: # BB#0:
; SSE2-X64-NEXT: movd %xmm0, %eax
; SSE2-X64-NEXT: movw %ax, (%rdi)
; SSE2-X64-NEXT: retq
;
; SSE41-X32-LABEL: extract_i16_0:
; SSE41-X32: # BB#0:
; SSE41-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE41-X32-NEXT: pextrw $0, %xmm0, (%eax)
; SSE41-X32-NEXT: retl
;
; SSE41-X64-LABEL: extract_i16_0:
; SSE41-X64: # BB#0:
; SSE41-X64-NEXT: pextrw $0, %xmm0, (%rdi)
; SSE41-X64-NEXT: retq
;
; AVX-X32-LABEL: extract_i16_0:
; AVX-X32: # BB#0:
; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; AVX-X32-NEXT: vpextrw $0, %xmm0, (%eax)
; AVX-X32-NEXT: retl
;
; AVX-X64-LABEL: extract_i16_0:
; AVX-X64: # BB#0:
; AVX-X64-NEXT: vpextrw $0, %xmm0, (%rdi)
; AVX-X64-NEXT: retq
[X86][SSE] Regenerate extraction+store memop tests Added tests for SSE2 as well as SSE41+AVX llvm-svn: 275876
2016-07-19 02:44:01 +08:00
%vecext = extractelement <8 x i16> %foo, i32 0
store i16 %vecext, i16* %dst, align 1
ret void
}
[X86][SSE] Add more thorough extract to store tests Added v4i32 and v2i64 tests and test on i686 as well as x86_64. llvm-svn: 294946
2017-02-13 21:40:12 +08:00
define void @extract_i16_7(i16* nocapture %dst, <8 x i16> %foo) nounwind {
; SSE2-X32-LABEL: extract_i16_7:
; SSE2-X32: # BB#0:
; SSE2-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE2-X32-NEXT: pextrw $7, %xmm0, %ecx
; SSE2-X32-NEXT: movw %cx, (%eax)
; SSE2-X32-NEXT: retl
;
; SSE2-X64-LABEL: extract_i16_7:
; SSE2-X64: # BB#0:
; SSE2-X64-NEXT: pextrw $7, %xmm0, %eax
; SSE2-X64-NEXT: movw %ax, (%rdi)
; SSE2-X64-NEXT: retq
;
; SSE41-X32-LABEL: extract_i16_7:
; SSE41-X32: # BB#0:
; SSE41-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE41-X32-NEXT: pextrw $7, %xmm0, (%eax)
; SSE41-X32-NEXT: retl
;
; SSE41-X64-LABEL: extract_i16_7:
; SSE41-X64: # BB#0:
; SSE41-X64-NEXT: pextrw $7, %xmm0, (%rdi)
; SSE41-X64-NEXT: retq
;
; AVX-X32-LABEL: extract_i16_7:
; AVX-X32: # BB#0:
; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; AVX-X32-NEXT: vpextrw $7, %xmm0, (%eax)
; AVX-X32-NEXT: retl
;
; AVX-X64-LABEL: extract_i16_7:
; AVX-X64: # BB#0:
; AVX-X64-NEXT: vpextrw $7, %xmm0, (%rdi)
; AVX-X64-NEXT: retq
SelectionDAG: Handle out-of-bounds index in extract vector element Summary: This patch correctly handles undef case of EXTRACT_VECTOR_ELT node where the element index is constant and not less than vector size. Test Plan: CodeGen for X86 test included. Also one incorrect regression test fixed. Reviewers: qcolombet, chandlerc, hfinkel Reviewed By: hfinkel Subscribers: hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D9250 llvm-svn: 236584
2015-05-06 18:19:14 +08:00
%vecext = extractelement <8 x i16> %foo, i32 7
store i16 %vecext, i16* %dst, align 1
ret void
}
[X86][SSE] Add more thorough extract to store tests Added v4i32 and v2i64 tests and test on i686 as well as x86_64. llvm-svn: 294946
2017-02-13 21:40:12 +08:00
define void @extract_i32_0(i32* nocapture %dst, <4 x i32> %foo) nounwind {
; SSE-X32-LABEL: extract_i32_0:
; SSE-X32: # BB#0:
; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-X32-NEXT: movss %xmm0, (%eax)
; SSE-X32-NEXT: retl
;
; SSE-X64-LABEL: extract_i32_0:
; SSE-X64: # BB#0:
; SSE-X64-NEXT: movss %xmm0, (%rdi)
; SSE-X64-NEXT: retq
;
; AVX-X32-LABEL: extract_i32_0:
; AVX-X32: # BB#0:
; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; AVX-X32-NEXT: vmovss %xmm0, (%eax)
; AVX-X32-NEXT: retl
;
; AVX-X64-LABEL: extract_i32_0:
; AVX-X64: # BB#0:
; AVX-X64-NEXT: vmovss %xmm0, (%rdi)
; AVX-X64-NEXT: retq
%vecext = extractelement <4 x i32> %foo, i32 0
store i32 %vecext, i32* %dst, align 1
ret void
}
define void @extract_i32_3(i32* nocapture %dst, <4 x i32> %foo) nounwind {
; SSE2-X32-LABEL: extract_i32_3:
; SSE2-X32: # BB#0:
; SSE2-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE2-X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
; SSE2-X32-NEXT: movd %xmm0, (%eax)
; SSE2-X32-NEXT: retl
;
; SSE2-X64-LABEL: extract_i32_3:
; SSE2-X64: # BB#0:
; SSE2-X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
; SSE2-X64-NEXT: movd %xmm0, (%rdi)
; SSE2-X64-NEXT: retq
;
; SSE41-X32-LABEL: extract_i32_3:
; SSE41-X32: # BB#0:
; SSE41-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE41-X32-NEXT: pextrd $3, %xmm0, (%eax)
; SSE41-X32-NEXT: retl
;
; SSE41-X64-LABEL: extract_i32_3:
; SSE41-X64: # BB#0:
; SSE41-X64-NEXT: pextrd $3, %xmm0, (%rdi)
; SSE41-X64-NEXT: retq
;
; AVX-X32-LABEL: extract_i32_3:
; AVX-X32: # BB#0:
; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; AVX-X32-NEXT: vpextrd $3, %xmm0, (%eax)
; AVX-X32-NEXT: retl
;
; AVX-X64-LABEL: extract_i32_3:
; AVX-X64: # BB#0:
; AVX-X64-NEXT: vpextrd $3, %xmm0, (%rdi)
; AVX-X64-NEXT: retq
%vecext = extractelement <4 x i32> %foo, i32 3
store i32 %vecext, i32* %dst, align 1
ret void
}
define void @extract_i64_0(i64* nocapture %dst, <2 x i64> %foo) nounwind {
; SSE-X32-LABEL: extract_i64_0:
; SSE-X32: # BB#0:
; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-X32-NEXT: movlps %xmm0, (%eax)
; SSE-X32-NEXT: retl
;
; SSE-X64-LABEL: extract_i64_0:
; SSE-X64: # BB#0:
; SSE-X64-NEXT: movlps %xmm0, (%rdi)
; SSE-X64-NEXT: retq
;
; AVX-X32-LABEL: extract_i64_0:
; AVX-X32: # BB#0:
; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; AVX-X32-NEXT: vmovlps %xmm0, (%eax)
; AVX-X32-NEXT: retl
;
; AVX-X64-LABEL: extract_i64_0:
; AVX-X64: # BB#0:
; AVX-X64-NEXT: vmovlps %xmm0, (%rdi)
; AVX-X64-NEXT: retq
%vecext = extractelement <2 x i64> %foo, i32 0
store i64 %vecext, i64* %dst, align 1
ret void
}
define void @extract_i64_1(i64* nocapture %dst, <2 x i64> %foo) nounwind {
; SSE-X32-LABEL: extract_i64_1:
; SSE-X32: # BB#0:
; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-X32-NEXT: psrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
; SSE-X32-NEXT: movq %xmm0, (%eax)
; SSE-X32-NEXT: retl
;
; SSE2-X64-LABEL: extract_i64_1:
; SSE2-X64: # BB#0:
; SSE2-X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE2-X64-NEXT: movq %xmm0, (%rdi)
; SSE2-X64-NEXT: retq
;
; SSE41-X64-LABEL: extract_i64_1:
; SSE41-X64: # BB#0:
; SSE41-X64-NEXT: pextrq $1, %xmm0, (%rdi)
; SSE41-X64-NEXT: retq
;
; AVX-X32-LABEL: extract_i64_1:
; AVX-X32: # BB#0:
; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; AVX-X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX-X32-NEXT: vmovq %xmm0, (%eax)
; AVX-X32-NEXT: retl
;
; AVX-X64-LABEL: extract_i64_1:
; AVX-X64: # BB#0:
; AVX-X64-NEXT: vpextrq $1, %xmm0, (%rdi)
; AVX-X64-NEXT: retq
%vecext = extractelement <2 x i64> %foo, i32 1
store i64 %vecext, i64* %dst, align 1
ret void
}
define void @extract_i8_undef(i8* nocapture %dst, <16 x i8> %foo) nounwind {
; X32-LABEL: extract_i8_undef:
; X32: # BB#0:
; X32-NEXT: retl
;
; X64-LABEL: extract_i8_undef:
; X64: # BB#0:
; X64-NEXT: retq
SelectionDAG: Handle out-of-bounds index in extract vector element Summary: This patch correctly handles undef case of EXTRACT_VECTOR_ELT node where the element index is constant and not less than vector size. Test Plan: CodeGen for X86 test included. Also one incorrect regression test fixed. Reviewers: qcolombet, chandlerc, hfinkel Reviewed By: hfinkel Subscribers: hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D9250 llvm-svn: 236584
2015-05-06 18:19:14 +08:00
%vecext = extractelement <16 x i8> %foo, i32 16 ; undef
store i8 %vecext, i8* %dst, align 1
ret void
}
[X86][SSE] Add more thorough extract to store tests Added v4i32 and v2i64 tests and test on i686 as well as x86_64. llvm-svn: 294946
2017-02-13 21:40:12 +08:00
define void @extract_i16_undef(i16* nocapture %dst, <8 x i16> %foo) nounwind {
; X32-LABEL: extract_i16_undef:
; X32: # BB#0:
; X32-NEXT: retl
;
; X64-LABEL: extract_i16_undef:
; X64: # BB#0:
; X64-NEXT: retq
SelectionDAG: Handle out-of-bounds index in extract vector element Summary: This patch correctly handles undef case of EXTRACT_VECTOR_ELT node where the element index is constant and not less than vector size. Test Plan: CodeGen for X86 test included. Also one incorrect regression test fixed. Reviewers: qcolombet, chandlerc, hfinkel Reviewed By: hfinkel Subscribers: hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D9250 llvm-svn: 236584
2015-05-06 18:19:14 +08:00
%vecext = extractelement <8 x i16> %foo, i32 9 ; undef
X86: Resolve a long standing FIXME and properly isel pextr[bw]. Generalize the AArch64 .td nodes for AssertZext and AssertSext. Use them to match the relevant pextr store instructions. The test widen_load-2.ll requires a slight change because with the stores gone, the remaining instructions are scheduled in a different order. Add test cases for SSE4 and AVX variants. Resolves rdar://13414672. Patch by Adam Nemet <anemet@apple.com>. llvm-svn: 200957
2014-02-07 08:16:33 +08:00
store i16 %vecext, i16* %dst, align 1
ret void
}
[X86][SSE] Add more thorough extract to store tests Added v4i32 and v2i64 tests and test on i686 as well as x86_64. llvm-svn: 294946
2017-02-13 21:40:12 +08:00
define void @extract_i32_undef(i32* nocapture %dst, <4 x i32> %foo) nounwind {
; X32-LABEL: extract_i32_undef:
; X32: # BB#0:
; X32-NEXT: retl
;
; X64-LABEL: extract_i32_undef:
; X64: # BB#0:
; X64-NEXT: retq
%vecext = extractelement <4 x i32> %foo, i32 6 ; undef
store i32 %vecext, i32* %dst, align 1
ret void
}
define void @extract_i64_undef(i64* nocapture %dst, <2 x i64> %foo) nounwind {
; X32-LABEL: extract_i64_undef:
; X32: # BB#0:
; X32-NEXT: retl
;
; X64-LABEL: extract_i64_undef:
; X64: # BB#0:
; X64-NEXT: retq
%vecext = extractelement <2 x i64> %foo, i32 2 ; undef
store i64 %vecext, i64* %dst, align 1
ret void
}