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llvm-project/llvm/test/CodeGen/Thumb2/mve-minmax.ll

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[ARM] MVE minnm and maxnm instructions This adds the patterns for minnm and maxnm from the fminnum and fmaxnum nodes, similar to scalar types. Original patch by Simon Tatham Differential Revision: https://reviews.llvm.org/D63870 llvm-svn: 366002
2019-07-13 22:29:02 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
[ARM] MVE integer min and max This simply makes the MVE integer min and max instructions legal and adds the relevant patterns for them. Differential Revision: https://reviews.llvm.org/D64026 llvm-svn: 366004
2019-07-13 22:48:54 +08:00
define arm_aapcs_vfpcc <16 x i8> @smin_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
; CHECK-LABEL: smin_v16i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmin.s8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = icmp slt <16 x i8> %s1, %s2
%1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2
ret <16 x i8> %1
}
define arm_aapcs_vfpcc <8 x i16> @smin_v8i16(<8 x i16> %s1, <8 x i16> %s2) {
; CHECK-LABEL: smin_v8i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmin.s16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = icmp slt <8 x i16> %s1, %s2
%1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2
ret <8 x i16> %1
}
define arm_aapcs_vfpcc <4 x i32> @smin_v4i32(<4 x i32> %s1, <4 x i32> %s2) {
; CHECK-LABEL: smin_v4i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmin.s32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = icmp slt <4 x i32> %s1, %s2
%1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
ret <4 x i32> %1
}
define arm_aapcs_vfpcc <16 x i8> @umin_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
; CHECK-LABEL: umin_v16i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmin.u8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = icmp ult <16 x i8> %s1, %s2
%1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2
ret <16 x i8> %1
}
define arm_aapcs_vfpcc <8 x i16> @umin_v8i16(<8 x i16> %s1, <8 x i16> %s2) {
; CHECK-LABEL: umin_v8i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmin.u16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = icmp ult <8 x i16> %s1, %s2
%1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2
ret <8 x i16> %1
}
define arm_aapcs_vfpcc <4 x i32> @umin_v4i32(<4 x i32> %s1, <4 x i32> %s2) {
; CHECK-LABEL: umin_v4i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmin.u32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = icmp ult <4 x i32> %s1, %s2
%1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
ret <4 x i32> %1
}
define arm_aapcs_vfpcc <16 x i8> @smax_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
; CHECK-LABEL: smax_v16i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmax.s8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = icmp sgt <16 x i8> %s1, %s2
%1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2
ret <16 x i8> %1
}
define arm_aapcs_vfpcc <8 x i16> @smax_v8i16(<8 x i16> %s1, <8 x i16> %s2) {
; CHECK-LABEL: smax_v8i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmax.s16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = icmp sgt <8 x i16> %s1, %s2
%1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2
ret <8 x i16> %1
}
define arm_aapcs_vfpcc <4 x i32> @smax_v4i32(<4 x i32> %s1, <4 x i32> %s2) {
; CHECK-LABEL: smax_v4i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmax.s32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = icmp sgt <4 x i32> %s1, %s2
%1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
ret <4 x i32> %1
}
define arm_aapcs_vfpcc <16 x i8> @umax_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
; CHECK-LABEL: umax_v16i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmax.u8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = icmp ugt <16 x i8> %s1, %s2
%1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2
ret <16 x i8> %1
}
define arm_aapcs_vfpcc <8 x i16> @umax_v8i16(<8 x i16> %s1, <8 x i16> %s2) {
; CHECK-LABEL: umax_v8i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmax.u16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = icmp ugt <8 x i16> %s1, %s2
%1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2
ret <8 x i16> %1
}
define arm_aapcs_vfpcc <4 x i32> @umax_v4i32(<4 x i32> %s1, <4 x i32> %s2) {
; CHECK-LABEL: umax_v4i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmax.u32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = icmp ugt <4 x i32> %s1, %s2
%1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
ret <4 x i32> %1
}
[ARM] MVE minnm and maxnm instructions This adds the patterns for minnm and maxnm from the fminnum and fmaxnum nodes, similar to scalar types. Original patch by Simon Tatham Differential Revision: https://reviews.llvm.org/D63870 llvm-svn: 366002
2019-07-13 22:29:02 +08:00
define arm_aapcs_vfpcc <4 x float> @maxnm_float32_t(<4 x float> %src1, <4 x float> %src2) {
; CHECK-MVE-LABEL: maxnm_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmaxnm.f32 s11, s7, s3
; CHECK-MVE-NEXT: vmaxnm.f32 s10, s6, s2
; CHECK-MVE-NEXT: vmaxnm.f32 s9, s5, s1
; CHECK-MVE-NEXT: vmaxnm.f32 s8, s4, s0
; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: maxnm_float32_t:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmaxnm.f32 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr
entry:
%cmp = fcmp fast ogt <4 x float> %src2, %src1
%0 = select <4 x i1> %cmp, <4 x float> %src2, <4 x float> %src1
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @minnm_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-MVE-LABEL: minnm_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov.u16 r0, q0[0]
; CHECK-MVE-NEXT: vmov.u16 r1, q0[1]
; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[0]
; CHECK-MVE-NEXT: vmov s10, r0
; CHECK-MVE-NEXT: vmov.u16 r2, q1[1]
; CHECK-MVE-NEXT: vminnm.f16 s8, s10, s8
; CHECK-MVE-NEXT: vmov s10, r2
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmov s8, r1
; CHECK-MVE-NEXT: vminnm.f16 s8, s10, s8
; CHECK-MVE-NEXT: vmov r1, s8
; CHECK-MVE-NEXT: vmov.16 q2[0], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[2]
; CHECK-MVE-NEXT: vmov.16 q2[1], r1
; CHECK-MVE-NEXT: vmov s12, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[2]
; CHECK-MVE-NEXT: vmov s14, r0
; CHECK-MVE-NEXT: vminnm.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmov.16 q2[2], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[3]
; CHECK-MVE-NEXT: vmov s12, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[3]
; CHECK-MVE-NEXT: vmov s14, r0
; CHECK-MVE-NEXT: vminnm.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmov.16 q2[3], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[4]
; CHECK-MVE-NEXT: vmov s12, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[4]
; CHECK-MVE-NEXT: vmov s14, r0
; CHECK-MVE-NEXT: vminnm.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmov.16 q2[4], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[5]
; CHECK-MVE-NEXT: vmov s12, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[5]
; CHECK-MVE-NEXT: vmov s14, r0
; CHECK-MVE-NEXT: vminnm.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmov.16 q2[5], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[6]
; CHECK-MVE-NEXT: vmov s12, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[6]
; CHECK-MVE-NEXT: vmov s14, r0
; CHECK-MVE-NEXT: vminnm.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmov.16 q2[6], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[7]
; CHECK-MVE-NEXT: vmov s0, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[7]
; CHECK-MVE-NEXT: vmov s2, r0
; CHECK-MVE-NEXT: vminnm.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q2[7], r0
; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: minnm_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vminnm.f16 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr
entry:
%cmp = fcmp fast ogt <8 x half> %src2, %src1
%0 = select <8 x i1> %cmp, <8 x half> %src1, <8 x half> %src2
ret <8 x half> %0
}