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llvm-project/llvm/test/CodeGen/ARM/ssat-upper.ll

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Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructions The mapping of these two intrinsics in ARMInstrInfo.td had a small omission which lead to their operands not being validated/transformed before being lowered into usat and ssat instructions. This can cause incorrect instructions to be emitted. I've also added tests for the remaining two saturating arithmatic intrinsics @llvm.arm.qadd and @llvm.arm.qsub as they are missing codegen tests. llvm-svn: 250697
2015-10-19 19:44:24 +08:00
; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructions for Thumb2 Summary: r250697 fixed the mapping for ARM mode. We have to do the same for Thumb2 otherwise the same llvm.arm.ssat() will generate different saturating amount for ARM and Thumb. r250697: http://reviews.llvm.org/rL250697 Reviewers: rmaprath Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D15653 llvm-svn: 256115
2015-12-20 14:41:44 +08:00
; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s
Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructions The mapping of these two intrinsics in ARMInstrInfo.td had a small omission which lead to their operands not being validated/transformed before being lowered into usat and ssat instructions. This can cause incorrect instructions to be emitted. I've also added tests for the remaining two saturating arithmatic intrinsics @llvm.arm.qadd and @llvm.arm.qsub as they are missing codegen tests. llvm-svn: 250697
2015-10-19 19:44:24 +08:00
; immediate argument > upper-bound
; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat
define i32 @ssat1() nounwind {
%tmp = call i32 @llvm.arm.ssat(i32 128, i32 33)
ret i32 %tmp
}
declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone