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llvm-project/llvm/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt

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Convert the uses of '|&' to use '2>&1 |' instead, which works on old versions of Bash. In addition, I can back out the change to the lit built-in shell test runner to support this. This should fix the majority of fallout on Darwin, but I suspect there will be a few straggling issues. llvm-svn: 159544
2012-07-03 02:37:59 +08:00
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as invalid instructions. llvm-svn: 129286
2011-04-12 02:34:12 +08:00
# Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7)
Continue to tighten decoding by performing more operand validation. llvm-svn: 137340
2011-08-12 04:21:46 +08:00
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as invalid instructions. llvm-svn: 129286
2011-04-12 02:34:12 +08:00
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
# -------------------------------------------------------------------------------------------------
Continue to tighten decoding by performing more operand validation. llvm-svn: 137340
2011-08-12 04:21:46 +08:00
#
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as invalid instructions. llvm-svn: 129286
2011-04-12 02:34:12 +08:00
# if t == 15 then UNPREDICTABLE
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. llvm-svn: 153089
2012-03-20 23:54:56 +08:00
# CHECK: warning: potentially undefined instruction encoding
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as invalid instructions. llvm-svn: 129286
2011-04-12 02:34:12 +08:00
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