llvm-project/llvm/test/CodeGen/X86/pr26652.ll

; RUN: llc < %s -march=x86
; PR26652

define <2 x i32> @test(<4 x i32> %a, <4 x i32> %b) {
entry:
  %0 = or <4 x i32> %a, %b
  %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
  ret <2 x i32> %1
}
Move test/CodeGen/Generic/pr26652.ll to test/CodeGen/X86/pr26652.ll and test it only on X86. llvm-svn: 261807 2016-02-25 08:12:18 +08:00			`; RUN: llc < %s -march=x86`
			`; PR26652`
Detecte vector reduction operations just before instruction selection. (This is the second attemp to commit this patch, after fixing pr26652 & pr26653). This patch detects vector reductions before instruction selection. Vector reductions are vectorized reduction operations, and for such operations we have freedom to reorganize the elements of the result as long as the reduction of them stay unchanged. This will enable some reduction pattern recognition during instruction combine such as SAD/dot-product on X86. A flag is added to SDNodeFlags to mark those vector reduction nodes to be checked during instruction combine. To detect those vector reductions, we search def-use chains starting from the given instruction, and check if all uses fall into two categories: 1. Reduction with another vector. 2. Reduction on all elements. in which 2 is detected by recognizing the pattern that the loop vectorizer generates to reduce all elements in the vector outside of the loop, which includes several ShuffleVector and one ExtractElement instructions. Differential revision: http://reviews.llvm.org/D15250 llvm-svn: 261804 2016-02-25 07:40:36 +08:00
			`define <2 x i32> @test(<4 x i32> %a, <4 x i32> %b) {`
			`entry:`
			`%0 = or <4 x i32> %a, %b`
			`%1 = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> <i32 2, i32 3>`
			`ret <2 x i32> %1`
			`}`