2017-05-03 23:42:29 +08:00
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//===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the operating system Host concept.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/Host.h"
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2017-11-11 01:10:57 +08:00
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#include "llvm/Support/TargetParser.h"
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2017-05-03 23:42:29 +08:00
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Config/config.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/FileSystem.h"
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#include "llvm/Support/MemoryBuffer.h"
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#include "llvm/Support/raw_ostream.h"
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#include <assert.h>
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#include <string.h>
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// Include the platform-specific parts of this class.
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#ifdef LLVM_ON_UNIX
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#include "Unix/Host.inc"
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#endif
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#ifdef LLVM_ON_WIN32
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#include "Windows/Host.inc"
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#endif
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#ifdef _MSC_VER
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#include <intrin.h>
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#endif
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#if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
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#include <mach/host_info.h>
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#include <mach/mach.h>
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#include <mach/mach_host.h>
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#include <mach/machine.h>
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#endif
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#define DEBUG_TYPE "host-detection"
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//===----------------------------------------------------------------------===//
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//
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// Implementations of the CPU detection routines
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//
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//===----------------------------------------------------------------------===//
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using namespace llvm;
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static std::unique_ptr<llvm::MemoryBuffer>
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LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() {
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llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
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llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
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if (std::error_code EC = Text.getError()) {
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llvm::errs() << "Can't read "
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<< "/proc/cpuinfo: " << EC.message() << "\n";
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return nullptr;
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}
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return std::move(*Text);
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}
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StringRef sys::detail::getHostCPUNameForPowerPC(
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const StringRef &ProcCpuinfoContent) {
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// Access to the Processor Version Register (PVR) on PowerPC is privileged,
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// and so we must use an operating-system interface to determine the current
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// processor type. On Linux, this is exposed through the /proc/cpuinfo file.
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const char *generic = "generic";
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// The cpu line is second (after the 'processor: 0' line), so if this
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// buffer is too small then something has changed (or is wrong).
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StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
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StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
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StringRef::const_iterator CIP = CPUInfoStart;
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StringRef::const_iterator CPUStart = 0;
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size_t CPULen = 0;
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// We need to find the first line which starts with cpu, spaces, and a colon.
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// After the colon, there may be some additional spaces and then the cpu type.
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while (CIP < CPUInfoEnd && CPUStart == 0) {
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if (CIP < CPUInfoEnd && *CIP == '\n')
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++CIP;
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if (CIP < CPUInfoEnd && *CIP == 'c') {
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++CIP;
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if (CIP < CPUInfoEnd && *CIP == 'p') {
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++CIP;
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if (CIP < CPUInfoEnd && *CIP == 'u') {
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++CIP;
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while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
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++CIP;
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if (CIP < CPUInfoEnd && *CIP == ':') {
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++CIP;
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while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
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++CIP;
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if (CIP < CPUInfoEnd) {
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CPUStart = CIP;
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while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
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*CIP != ',' && *CIP != '\n'))
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++CIP;
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CPULen = CIP - CPUStart;
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}
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}
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}
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}
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}
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if (CPUStart == 0)
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while (CIP < CPUInfoEnd && *CIP != '\n')
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++CIP;
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}
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if (CPUStart == 0)
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return generic;
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return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
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.Case("604e", "604e")
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.Case("604", "604")
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.Case("7400", "7400")
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.Case("7410", "7400")
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.Case("7447", "7400")
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.Case("7455", "7450")
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.Case("G4", "g4")
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.Case("POWER4", "970")
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.Case("PPC970FX", "970")
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.Case("PPC970MP", "970")
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.Case("G5", "g5")
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.Case("POWER5", "g5")
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.Case("A2", "a2")
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.Case("POWER6", "pwr6")
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.Case("POWER7", "pwr7")
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.Case("POWER8", "pwr8")
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.Case("POWER8E", "pwr8")
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.Case("POWER8NVL", "pwr8")
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.Case("POWER9", "pwr9")
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.Default(generic);
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}
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StringRef sys::detail::getHostCPUNameForARM(
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const StringRef &ProcCpuinfoContent) {
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// The cpuid register on arm is not accessible from user space. On Linux,
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// it is exposed through the /proc/cpuinfo file.
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// Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
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// in all cases.
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SmallVector<StringRef, 32> Lines;
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ProcCpuinfoContent.split(Lines, "\n");
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// Look for the CPU implementer line.
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StringRef Implementer;
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StringRef Hardware;
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for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
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if (Lines[I].startswith("CPU implementer"))
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Implementer = Lines[I].substr(15).ltrim("\t :");
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if (Lines[I].startswith("Hardware"))
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Hardware = Lines[I].substr(8).ltrim("\t :");
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}
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if (Implementer == "0x41") { // ARM Ltd.
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// MSM8992/8994 may give cpu part for the core that the kernel is running on,
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// which is undeterministic and wrong. Always return cortex-a53 for these SoC.
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if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
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return "cortex-a53";
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// Look for the CPU part line.
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for (unsigned I = 0, E = Lines.size(); I != E; ++I)
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if (Lines[I].startswith("CPU part"))
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// The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
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// values correspond to the "Part number" in the CP15/c0 register. The
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// contents are specified in the various processor manuals.
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return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
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.Case("0x926", "arm926ej-s")
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.Case("0xb02", "mpcore")
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.Case("0xb36", "arm1136j-s")
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.Case("0xb56", "arm1156t2-s")
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.Case("0xb76", "arm1176jz-s")
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.Case("0xc08", "cortex-a8")
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.Case("0xc09", "cortex-a9")
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.Case("0xc0f", "cortex-a15")
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.Case("0xc20", "cortex-m0")
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.Case("0xc23", "cortex-m3")
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.Case("0xc24", "cortex-m4")
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.Case("0xd04", "cortex-a35")
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.Case("0xd03", "cortex-a53")
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.Case("0xd07", "cortex-a57")
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.Case("0xd08", "cortex-a72")
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.Case("0xd09", "cortex-a73")
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.Default("generic");
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}
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if (Implementer == "0x51") // Qualcomm Technologies, Inc.
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// Look for the CPU part line.
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for (unsigned I = 0, E = Lines.size(); I != E; ++I)
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if (Lines[I].startswith("CPU part"))
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// The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
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// values correspond to the "Part number" in the CP15/c0 register. The
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// contents are specified in the various processor manuals.
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return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
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.Case("0x06f", "krait") // APQ8064
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.Case("0x201", "kryo")
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.Case("0x205", "kryo")
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2017-09-14 05:48:00 +08:00
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.Case("0x211", "kryo")
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.Case("0x800", "cortex-a73")
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.Case("0x801", "cortex-a73")
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2017-09-23 01:46:36 +08:00
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.Case("0xc00", "falkor")
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2017-09-25 22:05:00 +08:00
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.Case("0xc01", "saphira")
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2017-05-03 23:42:29 +08:00
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.Default("generic");
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2017-12-09 05:09:59 +08:00
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if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
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// The Exynos chips have a convoluted ID scheme that doesn't seem to follow
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// any predictive pattern across variants and parts.
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unsigned Variant = 0, Part = 0;
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// Look for the CPU variant line, whose value is a 1 digit hexadecimal
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// number, corresponding to the Variant bits in the CP15/C0 register.
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for (auto I : Lines)
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if (I.consume_front("CPU variant"))
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I.ltrim("\t :").getAsInteger(0, Variant);
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// Look for the CPU part line, whose value is a 3 digit hexadecimal
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// number, corresponding to the PartNum bits in the CP15/C0 register.
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for (auto I : Lines)
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if (I.consume_front("CPU part"))
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I.ltrim("\t :").getAsInteger(0, Part);
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unsigned Exynos = (Variant << 12) | Part;
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switch (Exynos) {
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default:
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// Default by falling through to Exynos M1.
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LLVM_FALLTHROUGH;
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case 0x1001:
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return "exynos-m1";
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case 0x4001:
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return "exynos-m2";
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}
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}
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2017-05-03 23:42:29 +08:00
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return "generic";
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}
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StringRef sys::detail::getHostCPUNameForS390x(
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const StringRef &ProcCpuinfoContent) {
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// STIDP is a privileged operation, so use /proc/cpuinfo instead.
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// The "processor 0:" line comes after a fair amount of other information,
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// including a cache breakdown, but this should be plenty.
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SmallVector<StringRef, 32> Lines;
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ProcCpuinfoContent.split(Lines, "\n");
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// Look for the CPU features.
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SmallVector<StringRef, 32> CPUFeatures;
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for (unsigned I = 0, E = Lines.size(); I != E; ++I)
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if (Lines[I].startswith("features")) {
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size_t Pos = Lines[I].find(":");
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if (Pos != StringRef::npos) {
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Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
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break;
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}
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}
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// We need to check for the presence of vector support independently of
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// the machine type, since we may only use the vector register set when
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// supported by the kernel (and hypervisor).
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bool HaveVectorSupport = false;
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for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
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if (CPUFeatures[I] == "vx")
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HaveVectorSupport = true;
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}
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// Now check the processor machine type.
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for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
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if (Lines[I].startswith("processor ")) {
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size_t Pos = Lines[I].find("machine = ");
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if (Pos != StringRef::npos) {
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Pos += sizeof("machine = ") - 1;
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unsigned int Id;
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if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
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2017-07-18 01:41:11 +08:00
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if (Id >= 3906 && HaveVectorSupport)
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return "z14";
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2017-05-03 23:42:29 +08:00
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if (Id >= 2964 && HaveVectorSupport)
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return "z13";
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if (Id >= 2827)
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return "zEC12";
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if (Id >= 2817)
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return "z196";
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}
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}
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break;
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}
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}
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return "generic";
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}
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2017-08-23 12:25:57 +08:00
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StringRef sys::detail::getHostCPUNameForBPF() {
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#if !defined(__linux__) || !defined(__x86_64__)
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return "generic";
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#else
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uint8_t insns[40] __attribute__ ((aligned (8))) =
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/* BPF_MOV64_IMM(BPF_REG_0, 0) */
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{ 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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/* BPF_MOV64_IMM(BPF_REG_2, 1) */
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0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
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/* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
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0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
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/* BPF_MOV64_IMM(BPF_REG_0, 1) */
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0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
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/* BPF_EXIT_INSN() */
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0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
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struct bpf_prog_load_attr {
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uint32_t prog_type;
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uint32_t insn_cnt;
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uint64_t insns;
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uint64_t license;
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uint32_t log_level;
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uint32_t log_size;
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uint64_t log_buf;
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uint32_t kern_version;
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uint32_t prog_flags;
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} attr = {};
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attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
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attr.insn_cnt = 5;
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attr.insns = (uint64_t)insns;
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attr.license = (uint64_t)"DUMMY";
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int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
|
2017-08-24 00:24:31 +08:00
|
|
|
if (fd >= 0) {
|
|
|
|
close(fd);
|
|
|
|
return "v2";
|
|
|
|
}
|
|
|
|
return "v1";
|
2017-08-23 12:25:57 +08:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-05-03 23:42:29 +08:00
|
|
|
#if defined(__i386__) || defined(_M_IX86) || \
|
|
|
|
defined(__x86_64__) || defined(_M_X64)
|
|
|
|
|
|
|
|
enum VendorSignatures {
|
|
|
|
SIG_INTEL = 0x756e6547 /* Genu */,
|
|
|
|
SIG_AMD = 0x68747541 /* Auth */
|
|
|
|
};
|
|
|
|
|
|
|
|
// The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
|
|
|
|
// Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
|
|
|
|
// support. Consequently, for i386, the presence of CPUID is checked first
|
|
|
|
// via the corresponding eflags bit.
|
|
|
|
// Removal of cpuid.h header motivated by PR30384
|
|
|
|
// Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
|
|
|
|
// or test-suite, but are used in external projects e.g. libstdcxx
|
|
|
|
static bool isCpuIdSupported() {
|
|
|
|
#if defined(__GNUC__) || defined(__clang__)
|
|
|
|
#if defined(__i386__)
|
|
|
|
int __cpuid_supported;
|
|
|
|
__asm__(" pushfl\n"
|
|
|
|
" popl %%eax\n"
|
|
|
|
" movl %%eax,%%ecx\n"
|
|
|
|
" xorl $0x00200000,%%eax\n"
|
|
|
|
" pushl %%eax\n"
|
|
|
|
" popfl\n"
|
|
|
|
" pushfl\n"
|
|
|
|
" popl %%eax\n"
|
|
|
|
" movl $0,%0\n"
|
|
|
|
" cmpl %%eax,%%ecx\n"
|
|
|
|
" je 1f\n"
|
|
|
|
" movl $1,%0\n"
|
|
|
|
"1:"
|
|
|
|
: "=r"(__cpuid_supported)
|
|
|
|
:
|
|
|
|
: "eax", "ecx");
|
|
|
|
if (!__cpuid_supported)
|
|
|
|
return false;
|
|
|
|
#endif
|
|
|
|
return true;
|
|
|
|
#endif
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
|
|
|
|
/// the specified arguments. If we can't run cpuid on the host, return true.
|
|
|
|
static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
|
|
|
|
unsigned *rECX, unsigned *rEDX) {
|
|
|
|
#if defined(__GNUC__) || defined(__clang__)
|
|
|
|
#if defined(__x86_64__)
|
|
|
|
// gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
|
|
|
|
// FIXME: should we save this for Clang?
|
|
|
|
__asm__("movq\t%%rbx, %%rsi\n\t"
|
|
|
|
"cpuid\n\t"
|
|
|
|
"xchgq\t%%rbx, %%rsi\n\t"
|
|
|
|
: "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
|
|
|
|
: "a"(value));
|
2017-07-10 14:04:11 +08:00
|
|
|
return false;
|
2017-05-03 23:42:29 +08:00
|
|
|
#elif defined(__i386__)
|
|
|
|
__asm__("movl\t%%ebx, %%esi\n\t"
|
|
|
|
"cpuid\n\t"
|
|
|
|
"xchgl\t%%ebx, %%esi\n\t"
|
|
|
|
: "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
|
|
|
|
: "a"(value));
|
2017-07-10 14:04:11 +08:00
|
|
|
return false;
|
2017-05-03 23:42:29 +08:00
|
|
|
#else
|
2017-07-10 14:04:11 +08:00
|
|
|
return true;
|
2017-05-03 23:42:29 +08:00
|
|
|
#endif
|
|
|
|
#elif defined(_MSC_VER)
|
|
|
|
// The MSVC intrinsic is portable across x86 and x64.
|
|
|
|
int registers[4];
|
|
|
|
__cpuid(registers, value);
|
|
|
|
*rEAX = registers[0];
|
|
|
|
*rEBX = registers[1];
|
|
|
|
*rECX = registers[2];
|
|
|
|
*rEDX = registers[3];
|
|
|
|
return false;
|
|
|
|
#else
|
|
|
|
return true;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
|
|
|
|
/// the 4 values in the specified arguments. If we can't run cpuid on the host,
|
|
|
|
/// return true.
|
|
|
|
static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
|
|
|
|
unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
|
|
|
|
unsigned *rEDX) {
|
|
|
|
#if defined(__GNUC__) || defined(__clang__)
|
2017-07-17 13:16:16 +08:00
|
|
|
#if defined(__x86_64__)
|
2017-07-10 14:09:22 +08:00
|
|
|
// gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
|
2017-05-03 23:42:29 +08:00
|
|
|
// FIXME: should we save this for Clang?
|
|
|
|
__asm__("movq\t%%rbx, %%rsi\n\t"
|
|
|
|
"cpuid\n\t"
|
|
|
|
"xchgq\t%%rbx, %%rsi\n\t"
|
|
|
|
: "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
|
|
|
|
: "a"(value), "c"(subleaf));
|
2017-07-10 14:04:11 +08:00
|
|
|
return false;
|
2017-07-17 13:16:16 +08:00
|
|
|
#elif defined(__i386__)
|
2017-05-03 23:42:29 +08:00
|
|
|
__asm__("movl\t%%ebx, %%esi\n\t"
|
|
|
|
"cpuid\n\t"
|
|
|
|
"xchgl\t%%ebx, %%esi\n\t"
|
|
|
|
: "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
|
|
|
|
: "a"(value), "c"(subleaf));
|
2017-07-10 14:04:11 +08:00
|
|
|
return false;
|
2017-05-03 23:42:29 +08:00
|
|
|
#else
|
2017-07-10 14:04:11 +08:00
|
|
|
return true;
|
2017-05-03 23:42:29 +08:00
|
|
|
#endif
|
2017-07-17 13:16:16 +08:00
|
|
|
#elif defined(_MSC_VER)
|
|
|
|
int registers[4];
|
|
|
|
__cpuidex(registers, value, subleaf);
|
|
|
|
*rEAX = registers[0];
|
|
|
|
*rEBX = registers[1];
|
|
|
|
*rECX = registers[2];
|
|
|
|
*rEDX = registers[3];
|
|
|
|
return false;
|
2017-05-03 23:42:29 +08:00
|
|
|
#else
|
|
|
|
return true;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-07-12 14:49:57 +08:00
|
|
|
// Read control register 0 (XCR0). Used to detect features such as AVX.
|
2017-05-03 23:42:29 +08:00
|
|
|
static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
|
|
|
|
#if defined(__GNUC__) || defined(__clang__)
|
|
|
|
// Check xgetbv; this uses a .byte sequence instead of the instruction
|
|
|
|
// directly because older assemblers do not include support for xgetbv and
|
|
|
|
// there is no easy way to conditionally compile based on the assembler used.
|
|
|
|
__asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
|
|
|
|
return false;
|
|
|
|
#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
|
|
|
|
unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
|
|
|
|
*rEAX = Result;
|
|
|
|
*rEDX = Result >> 32;
|
|
|
|
return false;
|
|
|
|
#else
|
|
|
|
return true;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
|
|
|
|
unsigned *Model) {
|
|
|
|
*Family = (EAX >> 8) & 0xf; // Bits 8 - 11
|
|
|
|
*Model = (EAX >> 4) & 0xf; // Bits 4 - 7
|
|
|
|
if (*Family == 6 || *Family == 0xf) {
|
|
|
|
if (*Family == 0xf)
|
|
|
|
// Examine extended family ID if family ID is F.
|
|
|
|
*Family += (EAX >> 20) & 0xff; // Bits 20 - 27
|
|
|
|
// Examine extended model ID if family ID is 6 or F.
|
|
|
|
*Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2017-07-08 13:16:14 +08:00
|
|
|
getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
|
|
|
|
unsigned Brand_id, unsigned Features,
|
2017-07-12 14:49:58 +08:00
|
|
|
unsigned Features2, unsigned *Type,
|
|
|
|
unsigned *Subtype) {
|
2017-05-03 23:42:29 +08:00
|
|
|
if (Brand_id != 0)
|
|
|
|
return;
|
|
|
|
switch (Family) {
|
|
|
|
case 3:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_i386;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 4:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_i486;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 5:
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_MMX)) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_PENTIUM_MMX;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
}
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_PENTIUM;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 6:
|
|
|
|
switch (Model) {
|
|
|
|
case 0x01: // Pentium Pro processor
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_PENTIUM_PRO;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
|
|
|
|
// model 03
|
|
|
|
case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
|
|
|
|
// model 05, and Intel Celeron processor, model 05
|
|
|
|
case 0x06: // Celeron processor, model 06
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_PENTIUM_II;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
|
|
|
|
// processor, model 07
|
|
|
|
case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
|
|
|
|
// model 08, and Celeron processor, model 08
|
|
|
|
case 0x0a: // Pentium III Xeon processor, model 0Ah
|
|
|
|
case 0x0b: // Pentium III processor, model 0Bh
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_PENTIUM_III;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
|
|
|
|
case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
|
|
|
|
// 0Dh. All processors are manufactured using the 90 nm process.
|
|
|
|
case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
|
|
|
|
// Integrated Processor with Intel QuickAssist Technology
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_PENTIUM_M;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
|
|
|
|
// 0Eh. All processors are manufactured using the 65 nm process.
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_CORE_DUO;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // yonah
|
|
|
|
case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
|
|
|
|
// processor, Intel Core 2 Quad processor, Intel Core 2 Quad
|
|
|
|
// mobile processor, Intel Core 2 Extreme processor, Intel
|
|
|
|
// Pentium Dual-Core processor, Intel Xeon processor, model
|
|
|
|
// 0Fh. All processors are manufactured using the 65 nm process.
|
|
|
|
case 0x16: // Intel Celeron processor model 16h. All processors are
|
|
|
|
// manufactured using the 65 nm process
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_CORE2; // "core2"
|
|
|
|
*Subtype = X86::INTEL_CORE2_65;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
|
|
|
|
// 17h. All processors are manufactured using the 45 nm process.
|
|
|
|
//
|
|
|
|
// 45nm: Penryn , Wolfdale, Yorkfield (XE)
|
|
|
|
case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
|
|
|
|
// the 45 nm process.
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_CORE2; // "penryn"
|
|
|
|
*Subtype = X86::INTEL_CORE2_45;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
|
|
|
|
// processors are manufactured using the 45 nm process.
|
|
|
|
case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
|
|
|
|
// As found in a Summer 2010 model iMac.
|
|
|
|
case 0x1f:
|
|
|
|
case 0x2e: // Nehalem EX
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_COREI7; // "nehalem"
|
|
|
|
*Subtype = X86::INTEL_COREI7_NEHALEM;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 0x25: // Intel Core i7, laptop version.
|
|
|
|
case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
|
|
|
|
// processors are manufactured using the 32 nm process.
|
|
|
|
case 0x2f: // Westmere EX
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_COREI7; // "westmere"
|
|
|
|
*Subtype = X86::INTEL_COREI7_WESTMERE;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 0x2a: // Intel Core i7 processor. All processors are manufactured
|
|
|
|
// using the 32 nm process.
|
|
|
|
case 0x2d:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_COREI7; //"sandybridge"
|
|
|
|
*Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 0x3a:
|
|
|
|
case 0x3e: // Ivy Bridge EP
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_COREI7; // "ivybridge"
|
|
|
|
*Subtype = X86::INTEL_COREI7_IVYBRIDGE;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
// Haswell:
|
|
|
|
case 0x3c:
|
|
|
|
case 0x3f:
|
|
|
|
case 0x45:
|
|
|
|
case 0x46:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_COREI7; // "haswell"
|
|
|
|
*Subtype = X86::INTEL_COREI7_HASWELL;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
// Broadwell:
|
|
|
|
case 0x3d:
|
|
|
|
case 0x47:
|
|
|
|
case 0x4f:
|
|
|
|
case 0x56:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_COREI7; // "broadwell"
|
|
|
|
*Subtype = X86::INTEL_COREI7_BROADWELL;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
// Skylake:
|
|
|
|
case 0x4e: // Skylake mobile
|
|
|
|
case 0x5e: // Skylake desktop
|
|
|
|
case 0x8e: // Kaby Lake mobile
|
|
|
|
case 0x9e: // Kaby Lake desktop
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_COREI7; // "skylake"
|
|
|
|
*Subtype = X86::INTEL_COREI7_SKYLAKE;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
// Skylake Xeon:
|
|
|
|
case 0x55:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_COREI7;
|
|
|
|
*Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
|
2017-11-15 14:02:42 +08:00
|
|
|
// Cannonlake:
|
|
|
|
case 0x66:
|
|
|
|
*Type = X86::INTEL_COREI7;
|
|
|
|
*Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake"
|
|
|
|
break;
|
|
|
|
|
2017-05-03 23:42:29 +08:00
|
|
|
case 0x1c: // Most 45 nm Intel Atom processors
|
|
|
|
case 0x26: // 45 nm Atom Lincroft
|
|
|
|
case 0x27: // 32 nm Atom Medfield
|
|
|
|
case 0x35: // 32 nm Atom Midview
|
|
|
|
case 0x36: // 32 nm Atom Midview
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_BONNELL;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // "bonnell"
|
|
|
|
|
|
|
|
// Atom Silvermont codes from the Intel software optimization guide.
|
|
|
|
case 0x37:
|
|
|
|
case 0x4a:
|
|
|
|
case 0x4d:
|
|
|
|
case 0x5a:
|
|
|
|
case 0x5d:
|
|
|
|
case 0x4c: // really airmont
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_SILVERMONT;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // "silvermont"
|
2017-06-29 18:00:33 +08:00
|
|
|
// Goldmont:
|
2017-11-15 14:02:43 +08:00
|
|
|
case 0x5c: // Apollo Lake
|
|
|
|
case 0x5f: // Denverton
|
|
|
|
case 0x7a: // Gemini Lake
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_GOLDMONT;
|
2017-06-29 18:00:33 +08:00
|
|
|
break; // "goldmont"
|
2017-05-03 23:42:29 +08:00
|
|
|
case 0x57:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_KNL; // knl
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
2017-10-14 02:10:17 +08:00
|
|
|
case 0x85:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_KNM; // knm
|
2017-10-14 02:10:17 +08:00
|
|
|
break;
|
2017-05-03 23:42:29 +08:00
|
|
|
|
|
|
|
default: // Unknown family 6 CPU, try to guess.
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_AVX512VBMI)) {
|
2017-11-15 14:02:42 +08:00
|
|
|
*Type = X86::INTEL_COREI7;
|
|
|
|
*Subtype = X86::INTEL_COREI7_CANNONLAKE;
|
2017-07-27 11:26:52 +08:00
|
|
|
break;
|
|
|
|
}
|
2017-11-15 14:02:42 +08:00
|
|
|
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_AVX512VL)) {
|
2017-11-15 14:02:42 +08:00
|
|
|
*Type = X86::INTEL_COREI7;
|
|
|
|
*Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_AVX512ER)) {
|
2017-11-15 14:02:42 +08:00
|
|
|
*Type = X86::INTEL_KNL; // knl
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features2 & (1 << (X86::FEATURE_CLFLUSHOPT - 32))) {
|
|
|
|
if (Features2 & (1 << (X86::FEATURE_SHA - 32))) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_GOLDMONT;
|
2017-07-27 11:26:52 +08:00
|
|
|
} else {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_COREI7;
|
|
|
|
*Subtype = X86::INTEL_COREI7_SKYLAKE;
|
2017-07-27 11:26:52 +08:00
|
|
|
}
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
}
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features2 & (1 << (X86::FEATURE_ADX - 32))) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_COREI7;
|
|
|
|
*Subtype = X86::INTEL_COREI7_BROADWELL;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
}
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_AVX2)) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_COREI7;
|
|
|
|
*Subtype = X86::INTEL_COREI7_HASWELL;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
}
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_AVX)) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_COREI7;
|
|
|
|
*Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
}
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_SSE4_2)) {
|
|
|
|
if (Features2 & (1 << (X86::FEATURE_MOVBE - 32))) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_SILVERMONT;
|
2017-05-03 23:42:29 +08:00
|
|
|
} else {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_COREI7;
|
|
|
|
*Subtype = X86::INTEL_COREI7_NEHALEM;
|
2017-05-03 23:42:29 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_SSE4_1)) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_CORE2; // "penryn"
|
|
|
|
*Subtype = X86::INTEL_CORE2_45;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
}
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_SSSE3)) {
|
|
|
|
if (Features2 & (1 << (X86::FEATURE_MOVBE - 32))) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_BONNELL; // "bonnell"
|
2017-05-03 23:42:29 +08:00
|
|
|
} else {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_CORE2; // "core2"
|
|
|
|
*Subtype = X86::INTEL_CORE2_65;
|
2017-05-03 23:42:29 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features2 & (1 << (X86::FEATURE_EM64T - 32))) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_CORE2; // "core2"
|
|
|
|
*Subtype = X86::INTEL_CORE2_65;
|
2017-11-03 03:13:32 +08:00
|
|
|
break;
|
|
|
|
}
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_SSE3)) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_CORE_DUO;
|
2017-11-03 03:13:32 +08:00
|
|
|
break;
|
2017-05-03 23:42:29 +08:00
|
|
|
}
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_SSE2)) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_PENTIUM_M;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
}
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_SSE)) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_PENTIUM_III;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
}
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_MMX)) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_PENTIUM_II;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
}
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_PENTIUM_PRO;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 15: {
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features2 & (1 << (X86::FEATURE_EM64T - 32))) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_NOCONA;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
2017-11-03 03:13:34 +08:00
|
|
|
}
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_SSE3)) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_PRESCOTT;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
}
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::INTEL_PENTIUM_IV;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
break; /*"generic"*/
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-07-08 14:44:34 +08:00
|
|
|
static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
|
|
|
|
unsigned Features, unsigned *Type,
|
2017-05-03 23:42:29 +08:00
|
|
|
unsigned *Subtype) {
|
|
|
|
// FIXME: this poorly matches the generated SubtargetFeatureKV table. There
|
|
|
|
// appears to be no way to generate the wide variety of AMD-specific targets
|
|
|
|
// from the information returned from CPUID.
|
|
|
|
switch (Family) {
|
|
|
|
case 4:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::AMD_i486;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 5:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::AMDPENTIUM;
|
2017-05-03 23:42:29 +08:00
|
|
|
switch (Model) {
|
|
|
|
case 6:
|
|
|
|
case 7:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Subtype = X86::AMDPENTIUM_K6;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // "k6"
|
|
|
|
case 8:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Subtype = X86::AMDPENTIUM_K62;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // "k6-2"
|
|
|
|
case 9:
|
|
|
|
case 13:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Subtype = X86::AMDPENTIUM_K63;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // "k6-3"
|
|
|
|
case 10:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Subtype = X86::AMDPENTIUM_GEODE;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // "geode"
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 6:
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_SSE)) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::AMD_ATHLON_XP;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // "athlon-xp"
|
|
|
|
}
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::AMD_ATHLON;
|
2017-07-13 14:34:10 +08:00
|
|
|
break; // "athlon"
|
2017-05-03 23:42:29 +08:00
|
|
|
case 15:
|
2017-11-22 07:36:42 +08:00
|
|
|
if (Features & (1 << X86::FEATURE_SSE3)) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::AMD_K8SSE3;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // "k8-sse3"
|
|
|
|
}
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::AMD_K8;
|
2017-07-13 14:34:10 +08:00
|
|
|
break; // "k8"
|
2017-05-03 23:42:29 +08:00
|
|
|
case 16:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::AMDFAM10H; // "amdfam10"
|
2017-05-03 23:42:29 +08:00
|
|
|
switch (Model) {
|
|
|
|
case 2:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Subtype = X86::AMDFAM10H_BARCELONA;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 4:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Subtype = X86::AMDFAM10H_SHANGHAI;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
case 8:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Subtype = X86::AMDFAM10H_ISTANBUL;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 20:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::AMD_BTVER1;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // "btver1";
|
|
|
|
case 21:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::AMDFAM15H;
|
2017-07-08 14:44:35 +08:00
|
|
|
if (Model >= 0x60 && Model <= 0x7f) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Subtype = X86::AMDFAM15H_BDVER4;
|
2017-07-12 14:49:56 +08:00
|
|
|
break; // "bdver4"; 60h-7Fh: Excavator
|
2017-05-03 23:42:29 +08:00
|
|
|
}
|
|
|
|
if (Model >= 0x30 && Model <= 0x3f) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Subtype = X86::AMDFAM15H_BDVER3;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // "bdver3"; 30h-3Fh: Steamroller
|
|
|
|
}
|
|
|
|
if (Model >= 0x10 && Model <= 0x1f) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Subtype = X86::AMDFAM15H_BDVER2;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // "bdver2"; 10h-1Fh: Piledriver
|
|
|
|
}
|
|
|
|
if (Model <= 0x0f) {
|
2017-11-11 01:10:57 +08:00
|
|
|
*Subtype = X86::AMDFAM15H_BDVER1;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // "bdver1"; 00h-0Fh: Bulldozer
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 22:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::AMD_BTVER2;
|
2017-05-03 23:42:29 +08:00
|
|
|
break; // "btver2"
|
|
|
|
case 23:
|
2017-11-11 01:10:57 +08:00
|
|
|
*Type = X86::AMDFAM17H;
|
|
|
|
*Subtype = X86::AMDFAM17H_ZNVER1;
|
2017-05-03 23:42:29 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break; // "generic"
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-07-12 14:49:58 +08:00
|
|
|
static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
|
|
|
|
unsigned *FeaturesOut,
|
|
|
|
unsigned *Features2Out) {
|
2017-05-03 23:42:29 +08:00
|
|
|
unsigned Features = 0;
|
2017-07-12 14:49:58 +08:00
|
|
|
unsigned Features2 = 0;
|
2017-07-08 13:16:14 +08:00
|
|
|
unsigned EAX, EBX;
|
2017-07-12 14:49:58 +08:00
|
|
|
|
|
|
|
if ((EDX >> 15) & 1)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_CMOV;
|
2017-07-12 14:49:58 +08:00
|
|
|
if ((EDX >> 23) & 1)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_MMX;
|
2017-07-12 14:49:58 +08:00
|
|
|
if ((EDX >> 25) & 1)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_SSE;
|
2017-07-12 14:49:58 +08:00
|
|
|
if ((EDX >> 26) & 1)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_SSE2;
|
2017-07-12 14:49:58 +08:00
|
|
|
|
|
|
|
if ((ECX >> 0) & 1)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_SSE3;
|
2017-07-12 14:49:58 +08:00
|
|
|
if ((ECX >> 1) & 1)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_PCLMUL;
|
2017-07-12 14:49:58 +08:00
|
|
|
if ((ECX >> 9) & 1)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_SSSE3;
|
2017-07-12 14:49:58 +08:00
|
|
|
if ((ECX >> 12) & 1)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_FMA;
|
2017-07-12 14:49:58 +08:00
|
|
|
if ((ECX >> 19) & 1)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_SSE4_1;
|
2017-07-12 14:49:58 +08:00
|
|
|
if ((ECX >> 20) & 1)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_SSE4_2;
|
2017-07-12 14:49:58 +08:00
|
|
|
if ((ECX >> 23) & 1)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_POPCNT;
|
2017-07-12 14:49:58 +08:00
|
|
|
if ((ECX >> 25) & 1)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AES;
|
2017-07-12 14:49:58 +08:00
|
|
|
|
|
|
|
if ((ECX >> 22) & 1)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features2 |= 1 << (X86::FEATURE_MOVBE - 32);
|
2017-05-03 23:42:29 +08:00
|
|
|
|
|
|
|
// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
|
|
|
|
// indicates that the AVX registers will be saved and restored on context
|
|
|
|
// switch, then we have full AVX support.
|
|
|
|
const unsigned AVXBits = (1 << 27) | (1 << 28);
|
|
|
|
bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
|
|
|
|
((EAX & 0x6) == 0x6);
|
|
|
|
bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
|
2017-07-12 14:49:58 +08:00
|
|
|
|
|
|
|
if (HasAVX)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX;
|
2017-07-12 14:49:58 +08:00
|
|
|
|
2017-05-03 23:42:29 +08:00
|
|
|
bool HasLeaf7 =
|
|
|
|
MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
|
2017-07-12 14:49:58 +08:00
|
|
|
|
|
|
|
if (HasLeaf7 && ((EBX >> 3) & 1))
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_BMI;
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX2;
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasLeaf7 && ((EBX >> 9) & 1))
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_BMI2;
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX512F;
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX512DQ;
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasLeaf7 && ((EBX >> 19) & 1))
|
2017-11-22 07:36:42 +08:00
|
|
|
Features2 |= 1 << (X86::FEATURE_ADX - 32);
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX512IFMA;
|
2017-07-27 11:26:52 +08:00
|
|
|
if (HasLeaf7 && ((EBX >> 23) & 1))
|
2017-11-22 07:36:42 +08:00
|
|
|
Features2 |= 1 << (X86::FEATURE_CLFLUSHOPT - 32);
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX512PF;
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX512ER;
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX512CD;
|
2017-07-27 11:26:52 +08:00
|
|
|
if (HasLeaf7 && ((EBX >> 29) & 1))
|
2017-11-22 07:36:42 +08:00
|
|
|
Features2 |= 1 << (X86::FEATURE_SHA - 32);
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX512BW;
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX512VL;
|
2017-07-12 14:49:58 +08:00
|
|
|
|
|
|
|
if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX512VBMI;
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX512VPOPCNTDQ;
|
2017-07-12 14:49:58 +08:00
|
|
|
|
|
|
|
if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX5124VNNIW;
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_AVX5124FMAPS;
|
2017-05-03 23:42:29 +08:00
|
|
|
|
2017-07-08 13:16:13 +08:00
|
|
|
unsigned MaxExtLevel;
|
|
|
|
getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
|
|
|
|
|
|
|
|
bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
|
|
|
|
!getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasExtLeaf1 && ((ECX >> 6) & 1))
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_SSE4_A;
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasExtLeaf1 && ((ECX >> 11) & 1))
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_XOP;
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasExtLeaf1 && ((ECX >> 16) & 1))
|
2017-11-22 07:36:42 +08:00
|
|
|
Features |= 1 << X86::FEATURE_FMA4;
|
2017-07-08 13:16:13 +08:00
|
|
|
|
2017-07-12 14:49:58 +08:00
|
|
|
if (HasExtLeaf1 && ((EDX >> 29) & 1))
|
2017-11-22 07:36:42 +08:00
|
|
|
Features2 |= 1 << (X86::FEATURE_EM64T - 32);
|
2017-07-12 14:49:58 +08:00
|
|
|
|
|
|
|
*FeaturesOut = Features;
|
|
|
|
*Features2Out = Features2;
|
2017-05-03 23:42:29 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
StringRef sys::getHostCPUName() {
|
|
|
|
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
|
|
|
|
unsigned MaxLeaf, Vendor;
|
|
|
|
|
|
|
|
#if defined(__GNUC__) || defined(__clang__)
|
|
|
|
//FIXME: include cpuid.h from clang or copy __get_cpuid_max here
|
|
|
|
// and simplify it to not invoke __cpuid (like cpu_model.c in
|
|
|
|
// compiler-rt/lib/builtins/cpu_model.c?
|
|
|
|
// Opting for the second option.
|
|
|
|
if(!isCpuIdSupported())
|
|
|
|
return "generic";
|
|
|
|
#endif
|
2017-07-08 13:16:13 +08:00
|
|
|
if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1)
|
2017-05-03 23:42:29 +08:00
|
|
|
return "generic";
|
2017-07-08 13:16:13 +08:00
|
|
|
getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
|
2017-05-03 23:42:29 +08:00
|
|
|
|
|
|
|
unsigned Brand_id = EBX & 0xff;
|
|
|
|
unsigned Family = 0, Model = 0;
|
2017-07-12 14:49:58 +08:00
|
|
|
unsigned Features = 0, Features2 = 0;
|
2017-05-03 23:42:29 +08:00
|
|
|
detectX86FamilyModel(EAX, &Family, &Model);
|
2017-07-12 14:49:58 +08:00
|
|
|
getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2);
|
2017-05-03 23:42:29 +08:00
|
|
|
|
2017-11-04 02:02:44 +08:00
|
|
|
unsigned Type = 0;
|
|
|
|
unsigned Subtype = 0;
|
2017-05-03 23:42:29 +08:00
|
|
|
|
|
|
|
if (Vendor == SIG_INTEL) {
|
2017-07-12 14:49:58 +08:00
|
|
|
getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features,
|
|
|
|
Features2, &Type, &Subtype);
|
2017-05-03 23:42:29 +08:00
|
|
|
} else if (Vendor == SIG_AMD) {
|
|
|
|
getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
|
|
|
|
}
|
2017-11-11 01:10:57 +08:00
|
|
|
|
|
|
|
// Check subtypes first since those are more specific.
|
|
|
|
#define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \
|
|
|
|
if (Subtype == X86::ENUM) \
|
|
|
|
return ARCHNAME;
|
|
|
|
#include "llvm/Support/X86TargetParser.def"
|
|
|
|
|
|
|
|
// Now check types.
|
|
|
|
#define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \
|
|
|
|
if (Type == X86::ENUM) \
|
|
|
|
return ARCHNAME;
|
|
|
|
#include "llvm/Support/X86TargetParser.def"
|
|
|
|
|
2017-05-03 23:42:29 +08:00
|
|
|
return "generic";
|
|
|
|
}
|
|
|
|
|
|
|
|
#elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
|
|
|
|
StringRef sys::getHostCPUName() {
|
|
|
|
host_basic_info_data_t hostInfo;
|
|
|
|
mach_msg_type_number_t infoCount;
|
|
|
|
|
|
|
|
infoCount = HOST_BASIC_INFO_COUNT;
|
|
|
|
host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
|
|
|
|
&infoCount);
|
|
|
|
|
|
|
|
if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
|
|
|
|
return "generic";
|
|
|
|
|
|
|
|
switch (hostInfo.cpu_subtype) {
|
|
|
|
case CPU_SUBTYPE_POWERPC_601:
|
|
|
|
return "601";
|
|
|
|
case CPU_SUBTYPE_POWERPC_602:
|
|
|
|
return "602";
|
|
|
|
case CPU_SUBTYPE_POWERPC_603:
|
|
|
|
return "603";
|
|
|
|
case CPU_SUBTYPE_POWERPC_603e:
|
|
|
|
return "603e";
|
|
|
|
case CPU_SUBTYPE_POWERPC_603ev:
|
|
|
|
return "603ev";
|
|
|
|
case CPU_SUBTYPE_POWERPC_604:
|
|
|
|
return "604";
|
|
|
|
case CPU_SUBTYPE_POWERPC_604e:
|
|
|
|
return "604e";
|
|
|
|
case CPU_SUBTYPE_POWERPC_620:
|
|
|
|
return "620";
|
|
|
|
case CPU_SUBTYPE_POWERPC_750:
|
|
|
|
return "750";
|
|
|
|
case CPU_SUBTYPE_POWERPC_7400:
|
|
|
|
return "7400";
|
|
|
|
case CPU_SUBTYPE_POWERPC_7450:
|
|
|
|
return "7450";
|
|
|
|
case CPU_SUBTYPE_POWERPC_970:
|
|
|
|
return "970";
|
|
|
|
default:;
|
|
|
|
}
|
|
|
|
|
|
|
|
return "generic";
|
|
|
|
}
|
|
|
|
#elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
|
|
|
|
StringRef sys::getHostCPUName() {
|
|
|
|
std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
|
|
|
|
const StringRef& Content = P ? P->getBuffer() : "";
|
|
|
|
return detail::getHostCPUNameForPowerPC(Content);
|
|
|
|
}
|
|
|
|
#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
|
|
|
|
StringRef sys::getHostCPUName() {
|
|
|
|
std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
|
|
|
|
const StringRef& Content = P ? P->getBuffer() : "";
|
|
|
|
return detail::getHostCPUNameForARM(Content);
|
|
|
|
}
|
|
|
|
#elif defined(__linux__) && defined(__s390x__)
|
|
|
|
StringRef sys::getHostCPUName() {
|
|
|
|
std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
|
|
|
|
const StringRef& Content = P ? P->getBuffer() : "";
|
|
|
|
return detail::getHostCPUNameForS390x(Content);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
StringRef sys::getHostCPUName() { return "generic"; }
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if defined(__linux__) && defined(__x86_64__)
|
|
|
|
// On Linux, the number of physical cores can be computed from /proc/cpuinfo,
|
|
|
|
// using the number of unique physical/core id pairs. The following
|
|
|
|
// implementation reads the /proc/cpuinfo format on an x86_64 system.
|
|
|
|
static int computeHostNumPhysicalCores() {
|
|
|
|
// Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
|
|
|
|
// mmapped because it appears to have 0 size.
|
|
|
|
llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
|
|
|
|
llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
|
|
|
|
if (std::error_code EC = Text.getError()) {
|
|
|
|
llvm::errs() << "Can't read "
|
|
|
|
<< "/proc/cpuinfo: " << EC.message() << "\n";
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
SmallVector<StringRef, 8> strs;
|
|
|
|
(*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1,
|
|
|
|
/*KeepEmpty=*/false);
|
|
|
|
int CurPhysicalId = -1;
|
|
|
|
int CurCoreId = -1;
|
|
|
|
SmallSet<std::pair<int, int>, 32> UniqueItems;
|
|
|
|
for (auto &Line : strs) {
|
|
|
|
Line = Line.trim();
|
|
|
|
if (!Line.startswith("physical id") && !Line.startswith("core id"))
|
|
|
|
continue;
|
|
|
|
std::pair<StringRef, StringRef> Data = Line.split(':');
|
|
|
|
auto Name = Data.first.trim();
|
|
|
|
auto Val = Data.second.trim();
|
|
|
|
if (Name == "physical id") {
|
|
|
|
assert(CurPhysicalId == -1 &&
|
|
|
|
"Expected a core id before seeing another physical id");
|
|
|
|
Val.getAsInteger(10, CurPhysicalId);
|
|
|
|
}
|
|
|
|
if (Name == "core id") {
|
|
|
|
assert(CurCoreId == -1 &&
|
|
|
|
"Expected a physical id before seeing another core id");
|
|
|
|
Val.getAsInteger(10, CurCoreId);
|
|
|
|
}
|
|
|
|
if (CurPhysicalId != -1 && CurCoreId != -1) {
|
|
|
|
UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId));
|
|
|
|
CurPhysicalId = -1;
|
|
|
|
CurCoreId = -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return UniqueItems.size();
|
|
|
|
}
|
|
|
|
#elif defined(__APPLE__) && defined(__x86_64__)
|
|
|
|
#include <sys/param.h>
|
|
|
|
#include <sys/sysctl.h>
|
|
|
|
|
|
|
|
// Gets the number of *physical cores* on the machine.
|
|
|
|
static int computeHostNumPhysicalCores() {
|
|
|
|
uint32_t count;
|
|
|
|
size_t len = sizeof(count);
|
|
|
|
sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0);
|
|
|
|
if (count < 1) {
|
|
|
|
int nm[2];
|
|
|
|
nm[0] = CTL_HW;
|
|
|
|
nm[1] = HW_AVAILCPU;
|
|
|
|
sysctl(nm, 2, &count, &len, NULL, 0);
|
|
|
|
if (count < 1)
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
// On other systems, return -1 to indicate unknown.
|
|
|
|
static int computeHostNumPhysicalCores() { return -1; }
|
|
|
|
#endif
|
|
|
|
|
|
|
|
int sys::getHostNumPhysicalCores() {
|
|
|
|
static int NumCores = computeHostNumPhysicalCores();
|
|
|
|
return NumCores;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(__i386__) || defined(_M_IX86) || \
|
|
|
|
defined(__x86_64__) || defined(_M_X64)
|
|
|
|
bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
|
|
|
|
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
|
|
|
|
unsigned MaxLevel;
|
|
|
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union {
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unsigned u[3];
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char c[12];
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} text;
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if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
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MaxLevel < 1)
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return false;
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getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
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2017-11-20 07:30:22 +08:00
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Features["cmov"] = (EDX >> 15) & 1;
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Features["mmx"] = (EDX >> 23) & 1;
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Features["sse"] = (EDX >> 25) & 1;
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Features["sse2"] = (EDX >> 26) & 1;
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Features["sse3"] = (ECX >> 0) & 1;
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Features["pclmul"] = (ECX >> 1) & 1;
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Features["ssse3"] = (ECX >> 9) & 1;
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Features["cx16"] = (ECX >> 13) & 1;
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2017-05-03 23:42:29 +08:00
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Features["sse4.1"] = (ECX >> 19) & 1;
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Features["sse4.2"] = (ECX >> 20) & 1;
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2017-11-20 07:30:22 +08:00
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Features["movbe"] = (ECX >> 22) & 1;
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2017-05-03 23:42:29 +08:00
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Features["popcnt"] = (ECX >> 23) & 1;
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2017-11-20 07:30:22 +08:00
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Features["aes"] = (ECX >> 25) & 1;
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Features["rdrnd"] = (ECX >> 30) & 1;
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2017-05-03 23:42:29 +08:00
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// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
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|
// indicates that the AVX registers will be saved and restored on context
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// switch, then we have full AVX support.
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bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
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!getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
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// AVX512 requires additional context to be saved by the OS.
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bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
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2017-11-20 07:30:22 +08:00
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Features["avx"] = HasAVXSave;
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Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
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// Only enable XSAVE if OS has enabled support for saving YMM state.
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Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
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Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
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|
2017-05-03 23:42:29 +08:00
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|
unsigned MaxExtLevel;
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getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
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bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
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!getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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2017-11-20 07:30:22 +08:00
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Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
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Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
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Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
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Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
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Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
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Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
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Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
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2017-05-03 23:42:29 +08:00
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Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
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bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
|
2017-11-20 07:49:19 +08:00
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|
|
!getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
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2017-05-03 23:42:29 +08:00
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Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
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|
bool HasLeaf7 =
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MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
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|
2017-11-20 07:30:22 +08:00
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Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
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Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
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Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
|
2017-05-03 23:42:29 +08:00
|
|
|
// AVX2 is only supported if we have the OS save support from AVX.
|
2017-11-20 07:30:22 +08:00
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|
Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
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Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
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|
|
Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
|
2017-05-03 23:42:29 +08:00
|
|
|
// AVX512 is only supported if the OS supports the context save for it.
|
2017-11-20 07:30:22 +08:00
|
|
|
Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
|
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|
|
Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
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|
|
Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
|
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|
|
Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
|
2017-05-03 23:42:29 +08:00
|
|
|
Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
|
2017-11-20 07:30:22 +08:00
|
|
|
Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
|
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|
|
Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
|
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|
|
Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
|
|
|
|
Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
|
|
|
|
Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
|
|
|
|
Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
|
|
|
|
Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
|
|
|
|
Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
|
|
|
|
|
|
|
|
Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1);
|
|
|
|
Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
|
2017-11-22 02:50:41 +08:00
|
|
|
Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
|
2017-11-21 17:48:44 +08:00
|
|
|
Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
|
2017-11-26 21:02:45 +08:00
|
|
|
Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
|
2017-11-26 17:36:41 +08:00
|
|
|
Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
|
2017-11-22 02:50:41 +08:00
|
|
|
Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
|
|
|
|
Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
|
|
|
|
Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
|
|
|
|
Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
|
2017-08-23 12:25:57 +08:00
|
|
|
Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
|
2018-01-19 07:52:31 +08:00
|
|
|
Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
|
|
|
|
|
|
|
|
Features["ibt"] = HasLeaf7 && ((EDX >> 20) & 1);
|
2017-11-26 21:02:45 +08:00
|
|
|
|
2017-05-03 23:42:29 +08:00
|
|
|
bool HasLeafD = MaxLevel >= 0xd &&
|
|
|
|
!getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
|
|
|
|
|
|
|
|
// Only enable XSAVE if OS has enabled support for saving YMM state.
|
2017-11-20 07:30:22 +08:00
|
|
|
Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
|
|
|
|
Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
|
|
|
|
Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
|
2017-05-03 23:42:29 +08:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
|
|
|
|
bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
|
|
|
|
std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
|
|
|
|
if (!P)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SmallVector<StringRef, 32> Lines;
|
|
|
|
P->getBuffer().split(Lines, "\n");
|
|
|
|
|
|
|
|
SmallVector<StringRef, 32> CPUFeatures;
|
|
|
|
|
|
|
|
// Look for the CPU features.
|
|
|
|
for (unsigned I = 0, E = Lines.size(); I != E; ++I)
|
|
|
|
if (Lines[I].startswith("Features")) {
|
|
|
|
Lines[I].split(CPUFeatures, ' ');
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(__aarch64__)
|
|
|
|
// Keep track of which crypto features we have seen
|
|
|
|
enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
|
|
|
|
uint32_t crypto = 0;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
|
|
|
|
StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
|
|
|
|
#if defined(__aarch64__)
|
|
|
|
.Case("asimd", "neon")
|
|
|
|
.Case("fp", "fp-armv8")
|
|
|
|
.Case("crc32", "crc")
|
|
|
|
#else
|
|
|
|
.Case("half", "fp16")
|
|
|
|
.Case("neon", "neon")
|
|
|
|
.Case("vfpv3", "vfp3")
|
|
|
|
.Case("vfpv3d16", "d16")
|
|
|
|
.Case("vfpv4", "vfp4")
|
|
|
|
.Case("idiva", "hwdiv-arm")
|
|
|
|
.Case("idivt", "hwdiv")
|
|
|
|
#endif
|
|
|
|
.Default("");
|
|
|
|
|
|
|
|
#if defined(__aarch64__)
|
|
|
|
// We need to check crypto separately since we need all of the crypto
|
|
|
|
// extensions to enable the subtarget feature
|
|
|
|
if (CPUFeatures[I] == "aes")
|
|
|
|
crypto |= CAP_AES;
|
|
|
|
else if (CPUFeatures[I] == "pmull")
|
|
|
|
crypto |= CAP_PMULL;
|
|
|
|
else if (CPUFeatures[I] == "sha1")
|
|
|
|
crypto |= CAP_SHA1;
|
|
|
|
else if (CPUFeatures[I] == "sha2")
|
|
|
|
crypto |= CAP_SHA2;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (LLVMFeatureStr != "")
|
|
|
|
Features[LLVMFeatureStr] = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(__aarch64__)
|
|
|
|
// If we have all crypto bits we can add the feature
|
|
|
|
if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
|
|
|
|
Features["crypto"] = true;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
|
|
|
|
#endif
|
|
|
|
|
|
|
|
std::string sys::getProcessTriple() {
|
2017-07-07 17:53:47 +08:00
|
|
|
std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
|
|
|
|
Triple PT(Triple::normalize(TargetTripleString));
|
2017-05-03 23:42:29 +08:00
|
|
|
|
|
|
|
if (sizeof(void *) == 8 && PT.isArch32Bit())
|
|
|
|
PT = PT.get64BitArchVariant();
|
|
|
|
if (sizeof(void *) == 4 && PT.isArch64Bit())
|
|
|
|
PT = PT.get32BitArchVariant();
|
|
|
|
|
|
|
|
return PT.str();
|
|
|
|
}
|