2021-05-06 06:13:14 +08:00
|
|
|
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
|
|
|
|
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
|
2015-05-20 12:24:19 +08:00
|
|
|
// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
|
2021-05-06 06:13:14 +08:00
|
|
|
// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
|
|
|
|
// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
|
|
|
|
// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4
|
2017-12-30 02:07:07 +08:00
|
|
|
|
2021-05-19 10:52:53 +08:00
|
|
|
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
2017-12-30 02:07:07 +08:00
|
|
|
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
|
2021-05-19 10:52:53 +08:00
|
|
|
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
|
|
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
|
|
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
2015-04-15 12:52:20 +08:00
|
|
|
// expected-no-diagnostics
|
|
|
|
#ifndef HEADER
|
|
|
|
#define HEADER
|
|
|
|
|
|
|
|
struct St {
|
|
|
|
int a, b;
|
|
|
|
St() : a(0), b(0) {}
|
|
|
|
St(const St &st) : a(st.a + st.b), b(0) {}
|
|
|
|
~St() {}
|
|
|
|
};
|
|
|
|
|
|
|
|
volatile int g = 1212;
|
2015-09-04 19:26:21 +08:00
|
|
|
volatile int &g1 = g;
|
2015-04-15 12:52:20 +08:00
|
|
|
|
|
|
|
template <class T>
|
|
|
|
struct S {
|
|
|
|
T f;
|
|
|
|
S(T a) : f(a + g) {}
|
|
|
|
S() : f(g) {}
|
|
|
|
S(const S &s, St t = St()) : f(s.f + t.a) {}
|
|
|
|
operator T() { return T(); }
|
|
|
|
~S() {}
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
template <typename T>
|
|
|
|
T tmain() {
|
|
|
|
S<T> test;
|
|
|
|
T t_var = T();
|
|
|
|
T vec[] = {1, 2};
|
|
|
|
S<T> s_arr[] = {1, 2};
|
2015-08-18 14:47:21 +08:00
|
|
|
S<T> &var = test;
|
2015-04-15 12:52:20 +08:00
|
|
|
#pragma omp parallel
|
|
|
|
#pragma omp for firstprivate(t_var, vec, s_arr, var)
|
2015-04-22 19:59:37 +08:00
|
|
|
for (int i = 0; i < 2; ++i) {
|
2015-04-15 12:52:20 +08:00
|
|
|
vec[i] = t_var;
|
|
|
|
s_arr[i] = var;
|
|
|
|
}
|
|
|
|
return T();
|
|
|
|
}
|
|
|
|
|
|
|
|
S<float> test;
|
|
|
|
int t_var = 333;
|
|
|
|
int vec[] = {1, 2};
|
|
|
|
S<float> s_arr[] = {1, 2};
|
|
|
|
S<float> var(3);
|
|
|
|
|
|
|
|
int main() {
|
2015-09-16 02:56:58 +08:00
|
|
|
static int sivar;
|
2015-04-15 12:52:20 +08:00
|
|
|
#ifdef LAMBDA
|
|
|
|
[&]() {
|
|
|
|
#pragma omp parallel
|
2015-09-16 02:56:58 +08:00
|
|
|
#pragma omp for firstprivate(g, g1, sivar)
|
2015-04-15 12:52:20 +08:00
|
|
|
for (int i = 0; i < 2; ++i) {
|
|
|
|
// Skip temp vars for loop
|
2021-05-06 06:13:14 +08:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2015-04-15 12:52:20 +08:00
|
|
|
g = 1;
|
2017-10-07 00:17:25 +08:00
|
|
|
g1 = 2;
|
|
|
|
sivar = 3;
|
2021-05-06 06:13:14 +08:00
|
|
|
|
2015-04-15 12:52:20 +08:00
|
|
|
[&]() {
|
2017-10-07 00:17:25 +08:00
|
|
|
g = 4;
|
|
|
|
g1 = 5;
|
|
|
|
sivar = 6;
|
2021-05-06 06:13:14 +08:00
|
|
|
|
2015-04-15 12:52:20 +08:00
|
|
|
}();
|
|
|
|
}
|
|
|
|
}();
|
|
|
|
return 0;
|
|
|
|
#elif defined(BLOCKS)
|
|
|
|
^{
|
|
|
|
#pragma omp parallel
|
2015-09-16 02:56:58 +08:00
|
|
|
#pragma omp for firstprivate(g, g1, sivar)
|
2015-04-15 12:52:20 +08:00
|
|
|
for (int i = 0; i < 2; ++i) {
|
|
|
|
// Skip temp vars for loop
|
2021-05-06 06:13:14 +08:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2015-04-15 12:52:20 +08:00
|
|
|
g = 1;
|
2015-09-04 19:26:21 +08:00
|
|
|
g1 =1;
|
2015-09-16 02:56:58 +08:00
|
|
|
sivar = 2;
|
2015-04-15 12:52:20 +08:00
|
|
|
^{
|
|
|
|
g = 2;
|
2015-09-04 19:26:21 +08:00
|
|
|
g1 = 2;
|
2015-09-16 02:56:58 +08:00
|
|
|
sivar = 4;
|
2015-04-15 12:52:20 +08:00
|
|
|
}();
|
|
|
|
}
|
|
|
|
}();
|
|
|
|
return 0;
|
|
|
|
#else
|
2015-09-16 02:56:58 +08:00
|
|
|
#pragma omp for firstprivate(t_var, vec, s_arr, var, sivar)
|
2015-04-22 19:59:37 +08:00
|
|
|
for (int i = 0; i < 2; ++i) {
|
2015-04-15 12:52:20 +08:00
|
|
|
vec[i] = t_var;
|
|
|
|
s_arr[i] = var;
|
2015-09-16 02:56:58 +08:00
|
|
|
sivar += i;
|
2015-04-15 12:52:20 +08:00
|
|
|
}
|
|
|
|
return tmain<int>();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
// Skip temp vars for loop
|
|
|
|
|
|
|
|
// firstprivate t_var(t_var)
|
|
|
|
|
|
|
|
// firstprivate vec(vec)
|
|
|
|
|
|
|
|
// firstprivate s_arr(s_arr)
|
|
|
|
|
|
|
|
// firstprivate var(var)
|
|
|
|
|
2015-09-16 02:56:58 +08:00
|
|
|
// firstprivate (sivar)
|
|
|
|
|
2015-04-15 12:52:20 +08:00
|
|
|
// Synchronization for initialization.
|
|
|
|
|
|
|
|
|
|
|
|
// ~(firstprivate var), ~(firstprivate s_arr)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Skip temp vars for loop
|
2021-05-06 06:13:14 +08:00
|
|
|
|
2015-09-10 16:12:02 +08:00
|
|
|
|
2015-04-15 12:52:20 +08:00
|
|
|
// firstprivate vec(vec)
|
|
|
|
|
|
|
|
// firstprivate s_arr(s_arr)
|
|
|
|
|
|
|
|
// firstprivate var(var)
|
|
|
|
|
2016-02-15 16:07:17 +08:00
|
|
|
// No synchronization for initialization.
|
2015-04-15 12:52:20 +08:00
|
|
|
|
|
|
|
|
|
|
|
// ~(firstprivate var), ~(firstprivate s_arr)
|
|
|
|
#endif
|
|
|
|
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
|
|
|
|
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK1-NEXT: entry:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
|
|
|
|
// CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
|
|
|
|
// CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK1-NEXT: entry:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
|
|
|
|
// CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
|
|
|
|
// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
|
|
|
|
// CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
|
|
|
|
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
|
|
|
// CHECK1: arraydestroy.body:
|
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
|
|
|
|
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
|
|
|
|
// CHECK1: arraydestroy.done1:
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
|
|
|
|
// CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
|
|
|
|
// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
|
|
|
|
// CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
|
|
|
|
// CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK1-NEXT: entry:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@main
|
|
|
|
// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
|
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
|
|
|
// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
|
|
|
|
// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
|
|
|
|
// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
|
|
|
|
// CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4
|
|
|
|
// CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
|
|
// CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4
|
|
|
|
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[T_VAR]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 bitcast ([2 x i32]* @vec to i8*), i64 8, i1 false)
|
|
|
|
// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
|
|
|
|
// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP3]]
|
|
|
|
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
|
|
|
|
// CHECK1: omp.arraycpy.body:
|
|
|
|
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
|
|
|
|
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
|
|
|
|
// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
|
|
|
|
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
|
|
|
|
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
|
|
|
|
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
|
|
|
|
// CHECK1: omp.arraycpy.done1:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]])
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], %struct.S* nonnull align 4 dereferenceable(4) @var, %struct.St* [[AGG_TMP2]])
|
|
|
|
// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
|
|
|
|
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[SIVAR]], align 4
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
|
|
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
|
|
// CHECK1: cond.true:
|
|
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
|
|
// CHECK1: cond.false:
|
|
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
|
|
// CHECK1: cond.end:
|
|
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
|
|
|
|
// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
|
|
// CHECK1: omp.inner.for.cond:
|
|
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
|
|
|
|
// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
|
|
|
|
// CHECK1: omp.inner.for.cond.cleanup:
|
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
|
|
|
|
// CHECK1: omp.inner.for.body:
|
|
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
|
|
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[T_VAR]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4
|
|
|
|
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
|
|
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
|
|
|
|
// CHECK1-NEXT: store i32 [[TMP11]], i32* [[ARRAYIDX]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
|
|
|
|
// CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64
|
|
|
|
// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM4]]
|
|
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8*
|
|
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[VAR]] to i8*
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[SIVAR]], align 4
|
|
|
|
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], [[TMP16]]
|
|
|
|
// CHECK1-NEXT: store i32 [[ADD6]], i32* [[SIVAR]], align 4
|
|
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
|
|
// CHECK1: omp.body.continue:
|
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
|
|
// CHECK1: omp.inner.for.inc:
|
|
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], 1
|
|
|
|
// CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
|
|
// CHECK1: omp.inner.for.end:
|
|
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
|
|
// CHECK1: omp.loop.exit:
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2
|
|
|
|
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
|
|
|
// CHECK1: arraydestroy.body:
|
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
|
|
|
|
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
|
|
|
|
// CHECK1: arraydestroy.done9:
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]])
|
|
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
|
|
|
|
// CHECK1-NEXT: ret i32 [[CALL]]
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
|
|
|
|
// CHECK1-SAME: () #[[ATTR6:[0-9]+]] {
|
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
|
|
|
|
// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
|
|
|
// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
|
|
|
|
// CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
|
|
|
|
// CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
|
|
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP1]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
|
|
// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
|
|
|
// CHECK1: arraydestroy.body:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
|
|
|
|
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
|
|
|
|
// CHECK1: arraydestroy.done1:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4
|
|
|
|
// CHECK1-NEXT: ret i32 [[TMP3]]
|
2021-05-06 06:13:14 +08:00
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
|
|
|
|
// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
|
|
|
|
// CHECK1-NEXT: store i32 0, i32* [[B]], align 4
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
|
|
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
|
|
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
|
|
|
|
// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
|
|
|
|
// CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR7:[0-9]+]] {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
|
|
|
|
// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
|
|
|
|
// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
|
|
|
|
// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
|
|
|
|
// CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
|
|
|
|
// CHECK1-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
|
|
|
|
// CHECK1-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
|
|
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8*
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 8, i1 false)
|
|
|
|
// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0*
|
|
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
|
|
|
|
// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]]
|
|
|
|
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1: omp.arraycpy.body:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
|
|
|
|
// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
|
|
|
|
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]]
|
|
|
|
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
|
|
|
|
// CHECK1: omp.arraycpy.done6:
|
|
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8
|
|
|
|
// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP10]], %struct.St* [[AGG_TMP8]])
|
|
|
|
// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP13]], 1
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
|
|
// CHECK1: cond.true:
|
|
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
|
|
// CHECK1: cond.false:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
|
|
// CHECK1: cond.end:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
|
|
// CHECK1: omp.inner.for.cond:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
|
|
// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1: omp.inner.for.cond.cleanup:
|
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
|
|
|
|
// CHECK1: omp.inner.for.body:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR3]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
|
|
|
|
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
|
|
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
|
|
|
|
// CHECK1-NEXT: store i32 [[TMP19]], i32* [[ARRAYIDX]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
|
|
|
|
// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP22]] to i64
|
|
|
|
// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
|
|
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8*
|
|
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[TMP21]] to i8*
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i64 4, i1 false)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
|
|
// CHECK1: omp.body.continue:
|
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
|
|
// CHECK1: omp.inner.for.inc:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP25]], 1
|
|
|
|
// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
|
|
// CHECK1: omp.inner.for.end:
|
|
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
|
|
// CHECK1: omp.loop.exit:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]])
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
|
|
|
|
// CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
|
|
|
// CHECK1: arraydestroy.body:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
|
|
|
|
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
|
|
|
|
// CHECK1: arraydestroy.done15:
|
|
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP30]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
|
|
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
|
|
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
|
|
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp
|
|
|
|
// CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: call void @__cxx_global_var_init()
|
|
|
|
// CHECK1-NEXT: call void @__cxx_global_var_init.1()
|
|
|
|
// CHECK1-NEXT: call void @__cxx_global_var_init.2()
|
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init
|
|
|
|
// CHECK2-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK2-NEXT: entry:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
|
|
|
|
// CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
|
|
|
|
// CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK2-NEXT: entry:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
|
|
|
|
// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
|
|
|
|
// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
|
|
|
|
// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
|
|
|
|
// CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
|
|
|
|
// CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
|
|
|
// CHECK2: arraydestroy.body:
|
|
|
|
// CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
|
|
|
// CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
|
|
|
|
// CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
|
|
|
|
// CHECK2: arraydestroy.done1:
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
|
|
|
|
// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
|
|
|
|
// CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
|
|
|
|
// CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
|
|
|
|
// CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK2-NEXT: entry:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@main
|
|
|
|
// CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
|
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
|
|
|
// CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
|
|
|
|
// CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
|
|
|
|
// CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
|
|
|
|
// CHECK2-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4
|
|
|
|
// CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
|
|
// CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4
|
|
|
|
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[T_VAR]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
|
|
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 bitcast ([2 x i32]* @vec to i8*), i64 8, i1 false)
|
|
|
|
// CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
|
|
|
|
// CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP3]]
|
|
|
|
// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
|
|
|
|
// CHECK2: omp.arraycpy.body:
|
|
|
|
// CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
|
|
|
|
// CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
|
|
|
|
// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
|
|
|
|
// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
|
|
|
|
// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
|
|
|
|
// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
|
|
|
|
// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
|
|
|
|
// CHECK2: omp.arraycpy.done1:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]])
|
|
|
|
// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], %struct.S* nonnull align 4 dereferenceable(4) @var, %struct.St* [[AGG_TMP2]])
|
|
|
|
// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
|
|
|
|
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[SIVAR]], align 4
|
|
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
|
|
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
|
|
// CHECK2: cond.true:
|
|
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
|
|
// CHECK2: cond.false:
|
|
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
|
|
// CHECK2: cond.end:
|
|
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
|
|
|
|
// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
|
|
// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
|
|
// CHECK2: omp.inner.for.cond:
|
|
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
|
|
|
|
// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
|
|
|
|
// CHECK2: omp.inner.for.cond.cleanup:
|
|
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
|
|
|
|
// CHECK2: omp.inner.for.body:
|
|
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
|
|
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[T_VAR]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4
|
|
|
|
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
|
|
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
|
|
|
|
// CHECK2-NEXT: store i32 [[TMP11]], i32* [[ARRAYIDX]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
|
|
|
|
// CHECK2-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64
|
|
|
|
// CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM4]]
|
|
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8*
|
|
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[VAR]] to i8*
|
|
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false)
|
|
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[SIVAR]], align 4
|
|
|
|
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], [[TMP16]]
|
|
|
|
// CHECK2-NEXT: store i32 [[ADD6]], i32* [[SIVAR]], align 4
|
|
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
|
|
// CHECK2: omp.body.continue:
|
|
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
|
|
// CHECK2: omp.inner.for.inc:
|
|
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], 1
|
|
|
|
// CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
|
|
// CHECK2: omp.inner.for.end:
|
|
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
|
|
// CHECK2: omp.loop.exit:
|
|
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2
|
|
|
|
// CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
|
|
|
// CHECK2: arraydestroy.body:
|
|
|
|
// CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
|
|
|
// CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
|
|
|
|
// CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
|
|
|
|
// CHECK2: arraydestroy.done9:
|
|
|
|
// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]])
|
|
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
|
|
|
|
// CHECK2-NEXT: ret i32 [[CALL]]
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
|
|
|
|
// CHECK2-SAME: () #[[ATTR6:[0-9]+]] {
|
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
|
|
|
|
// CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
|
|
|
// CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
|
|
|
|
// CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
|
|
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
|
|
|
|
// CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
|
|
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP1]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
|
|
// CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
|
|
|
// CHECK2: arraydestroy.body:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
|
|
|
|
// CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
|
|
|
|
// CHECK2: arraydestroy.done1:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4
|
|
|
|
// CHECK2-NEXT: ret i32 [[TMP3]]
|
2021-05-06 06:13:14 +08:00
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
|
|
|
|
// CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
|
|
|
|
// CHECK2-NEXT: store i32 0, i32* [[B]], align 4
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
|
|
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
|
|
// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
|
|
|
|
// CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
|
|
|
|
// CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR7:[0-9]+]] {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
|
|
|
|
// CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
|
|
|
|
// CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
|
|
|
|
// CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
|
|
|
|
// CHECK2-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
|
|
|
|
// CHECK2-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
|
|
|
|
// CHECK2-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
|
|
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
|
|
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8*
|
|
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 8, i1 false)
|
|
|
|
// CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0*
|
|
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
|
|
|
|
// CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]]
|
|
|
|
// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2: omp.arraycpy.body:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
|
|
|
|
// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
|
|
|
|
// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
|
|
|
|
// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]]
|
|
|
|
// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
|
|
|
|
// CHECK2: omp.arraycpy.done6:
|
|
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8
|
|
|
|
// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
|
|
|
|
// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP10]], %struct.St* [[AGG_TMP8]])
|
|
|
|
// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
|
|
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP13]], 1
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
|
|
// CHECK2: cond.true:
|
|
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
|
|
// CHECK2: cond.false:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
|
|
// CHECK2: cond.end:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
|
|
// CHECK2-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
|
|
// CHECK2: omp.inner.for.cond:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK2-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
|
|
// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2: omp.inner.for.cond.cleanup:
|
|
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
|
|
|
|
// CHECK2: omp.inner.for.body:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR3]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
|
|
|
|
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
|
|
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
|
|
|
|
// CHECK2-NEXT: store i32 [[TMP19]], i32* [[ARRAYIDX]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
|
|
|
|
// CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP22]] to i64
|
|
|
|
// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
|
|
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8*
|
|
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[TMP21]] to i8*
|
|
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i64 4, i1 false)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
|
|
// CHECK2: omp.body.continue:
|
|
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
|
|
// CHECK2: omp.inner.for.inc:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP25]], 1
|
|
|
|
// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
|
|
// CHECK2: omp.inner.for.end:
|
|
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
|
|
// CHECK2: omp.loop.exit:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4
|
|
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]])
|
|
|
|
// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
|
|
|
|
// CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
|
|
|
// CHECK2: arraydestroy.body:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
|
|
|
|
// CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
|
|
|
|
// CHECK2: arraydestroy.done15:
|
|
|
|
// CHECK2-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
|
|
|
|
// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP30]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
|
|
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
|
|
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
|
|
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
|
|
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
|
|
|
|
// CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp
|
|
|
|
// CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK2-NEXT: entry:
|
|
|
|
// CHECK2-NEXT: call void @__cxx_global_var_init()
|
|
|
|
// CHECK2-NEXT: call void @__cxx_global_var_init.1()
|
|
|
|
// CHECK2-NEXT: call void @__cxx_global_var_init.2()
|
|
|
|
// CHECK2-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
|
|
|
|
// CHECK3-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK3-NEXT: entry:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
|
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: entry:
|
|
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: entry:
|
|
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK3-NEXT: entry:
|
|
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
|
|
|
|
// CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4
|
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK3-NEXT: entry:
|
|
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
|
|
|
|
// CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK3-NEXT: entry:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
|
|
|
|
// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
|
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: entry:
|
|
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
|
|
|
|
// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
|
|
|
|
// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
|
|
|
|
// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK3-NEXT: entry:
|
|
|
|
// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
|
|
|
|
// CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
|
|
|
|
// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
|
|
|
// CHECK3: arraydestroy.body:
|
|
|
|
// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
|
|
|
// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
|
|
|
|
// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
|
|
|
|
// CHECK3: arraydestroy.done1:
|
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK3-NEXT: entry:
|
|
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
|
|
|
|
// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
|
|
|
|
// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
|
|
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
|
|
|
|
// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
|
|
|
|
// CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
|
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
|
|
|
|
// CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK3-NEXT: entry:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
|
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@main
|
|
|
|
// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
|
|
|
|
// CHECK3-NEXT: entry:
|
|
|
|
// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
|
|
|
|
// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
|
|
|
|
// CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: ret i32 0
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: entry:
|
|
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 8
|
|
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[G:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-NEXT: [[SIVAR3:%.*]] = alloca i32, align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
|
|
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** @g1, align 8
|
|
|
|
// CHECK3-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
|
|
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK3-NEXT: store i32 [[TMP2]], i32* [[G]], align 4
|
|
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[G1]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[SIVAR3]], align 4
|
|
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
|
|
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
|
|
// CHECK3: cond.true:
|
|
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
|
|
// CHECK3: cond.false:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
|
|
// CHECK3: cond.end:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
|
|
// CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
|
|
// CHECK3: omp.inner.for.cond:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK3-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
|
|
|
|
// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
2021-06-16 01:30:12 +08:00
|
|
|
// CHECK3: omp.inner.for.body:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
|
|
// CHECK3-NEXT: store i32 1, i32* [[G]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP2]], align 8
|
|
|
|
// CHECK3-NEXT: store volatile i32 2, i32* [[TMP13]], align 4
|
|
|
|
// CHECK3-NEXT: store i32 3, i32* [[SIVAR3]], align 4
|
|
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
|
|
|
|
// CHECK3-NEXT: store i32* [[G]], i32** [[TMP14]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
|
|
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[_TMP2]], align 8
|
|
|
|
// CHECK3-NEXT: store i32* [[TMP16]], i32** [[TMP15]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
|
|
|
|
// CHECK3-NEXT: store i32* [[SIVAR3]], i32** [[TMP17]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
|
|
// CHECK3: omp.body.continue:
|
|
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
|
|
// CHECK3: omp.inner.for.inc:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], 1
|
|
|
|
// CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
|
|
// CHECK3: omp.inner.for.end:
|
|
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
|
|
// CHECK3: omp.loop.exit:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
|
|
|
|
// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp
|
|
|
|
// CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK3-NEXT: entry:
|
|
|
|
// CHECK3-NEXT: call void @__cxx_global_var_init()
|
|
|
|
// CHECK3-NEXT: call void @__cxx_global_var_init.1()
|
|
|
|
// CHECK3-NEXT: call void @__cxx_global_var_init.2()
|
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init
|
|
|
|
// CHECK4-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK4-NEXT: entry:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
|
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: entry:
|
|
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: entry:
|
|
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK4-NEXT: entry:
|
|
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
|
|
|
|
// CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4
|
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK4-NEXT: entry:
|
|
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
|
|
|
|
// CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK4-NEXT: entry:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
|
|
|
|
// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
|
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: entry:
|
|
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
|
|
|
|
// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
|
|
|
|
// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
|
|
|
|
// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK4-NEXT: entry:
|
|
|
|
// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
|
|
|
|
// CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
|
|
|
|
// CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
|
|
|
// CHECK4: arraydestroy.body:
|
|
|
|
// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
|
|
|
// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
|
|
|
|
// CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
|
|
|
|
// CHECK4: arraydestroy.done1:
|
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
[OpenMP] Overhaul `declare target` handling
This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.
This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.
I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.
Highlights:
- new diagnosis for restrictions specificed in the standard,
- delayed emission of globals not mentioned in an explicit
list of a declare target,
- omission of `nohost` globals on the host and `host` globals on the
device,
- no explicit parsing of declarations in-between `omp [begin] declare
variant` and the corresponding end anymore, regular parsing instead,
- precedence for explicit mentions in `declare target` lists over
implicit mentions in the declaration-definition-seq, and
- `omp allocate` declarations will now replace an earlier emitted
global, if necessary.
---
Notes:
The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.
After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.
---
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D101030
2021-04-22 13:57:28 +08:00
|
|
|
// CHECK4-NEXT: entry:
|
|
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
|
|
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
|
|
|
|
// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
|
|
|
|
// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
|
|
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
|
|
|
|
// CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
|
|
|
|
// CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4
|
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
|
|
|
|
// CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK4-NEXT: entry:
|
2021-05-13 23:20:37 +08:00
|
|
|
// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
|
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@main
|
|
|
|
// CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
|
|
|
|
// CHECK4-NEXT: entry:
|
|
|
|
// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8
|
|
|
|
// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
|
|
// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0
|
|
|
|
// CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1
|
|
|
|
// CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2
|
|
|
|
// CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4
|
|
|
|
// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3
|
|
|
|
// CHECK4-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4
|
|
|
|
// CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5
|
|
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
|
|
|
|
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()*
|
|
|
|
// CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic*
|
|
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3
|
|
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8*
|
|
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)*
|
|
|
|
// CHECK4-NEXT: call void [[TMP5]](i8* [[TMP3]])
|
|
|
|
// CHECK4-NEXT: ret i32 0
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke
|
|
|
|
// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] {
|
|
|
|
// CHECK4-NEXT: entry:
|
|
|
|
// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8
|
|
|
|
// CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*
|
|
|
|
// CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5sivar)
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: entry:
|
|
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 8
|
|
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[G:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[G1:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: [[SIVAR3:%.*]] = alloca i32, align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, align 8
|
|
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** @g1, align 8
|
|
|
|
// CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
|
|
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK4-NEXT: store i32 [[TMP2]], i32* [[G]], align 4
|
|
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load volatile i32, i32* @g, align 4
|
|
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[G1]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[SIVAR3]], align 4
|
|
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
|
|
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
|
|
// CHECK4: cond.true:
|
|
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
|
|
// CHECK4: cond.false:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
|
|
// CHECK4: cond.end:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
|
|
// CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
|
|
// CHECK4: omp.inner.for.cond:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
|
|
// CHECK4-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
|
|
|
|
// CHECK4-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
2021-06-16 01:30:12 +08:00
|
|
|
// CHECK4: omp.inner.for.body:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
|
|
// CHECK4-NEXT: store i32 1, i32* [[G]], align 4
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP2]], align 8
|
|
|
|
// CHECK4-NEXT: store volatile i32 1, i32* [[TMP13]], align 4
|
|
|
|
// CHECK4-NEXT: store i32 2, i32* [[SIVAR3]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 0
|
|
|
|
// CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 1
|
|
|
|
// CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 2
|
|
|
|
// CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4
|
|
|
|
// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 3
|
|
|
|
// CHECK4-NEXT: store i8* bitcast (void (i8*)* @var_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 4
|
|
|
|
// CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 6
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[G]], align 4
|
|
|
|
// CHECK4-NEXT: store volatile i32 [[TMP14]], i32* [[BLOCK_CAPTURED]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 5
|
|
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[_TMP2]], align 8
|
|
|
|
// CHECK4-NEXT: store i32* [[TMP15]], i32** [[BLOCK_CAPTURED5]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 7
|
|
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR3]], align 4
|
|
|
|
// CHECK4-NEXT: store i32 [[TMP16]], i32* [[BLOCK_CAPTURED6]], align 4
|
|
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]] to void ()*
|
|
|
|
// CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP17]] to %struct.__block_literal_generic*
|
|
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3
|
|
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8*
|
|
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = load i8*, i8** [[TMP18]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8* [[TMP20]] to void (i8*)*
|
|
|
|
// CHECK4-NEXT: call void [[TMP21]](i8* [[TMP19]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
|
|
// CHECK4: omp.body.continue:
|
|
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
|
|
// CHECK4: omp.inner.for.inc:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
|
|
// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], 1
|
|
|
|
// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
|
|
// CHECK4: omp.inner.for.end:
|
|
|
|
// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
|
|
// CHECK4: omp.loop.exit:
|
2021-07-19 22:54:26 +08:00
|
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
|
|
|
|
// CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]])
|
2021-05-06 06:13:14 +08:00
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@var_block_invoke
|
|
|
|
// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] {
|
|
|
|
// CHECK4-NEXT: entry:
|
|
|
|
// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>*, align 8
|
|
|
|
// CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>*
|
|
|
|
// CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>** [[BLOCK_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 6
|
|
|
|
// CHECK4-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 5
|
|
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR1]], align 8
|
|
|
|
// CHECK4-NEXT: store i32 2, i32* [[TMP0]], align 4
|
|
|
|
// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 7
|
|
|
|
// CHECK4-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR2]], align 4
|
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp
|
|
|
|
// CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
|
|
|
|
// CHECK4-NEXT: entry:
|
|
|
|
// CHECK4-NEXT: call void @__cxx_global_var_init()
|
|
|
|
// CHECK4-NEXT: call void @__cxx_global_var_init.1()
|
|
|
|
// CHECK4-NEXT: call void @__cxx_global_var_init.2()
|
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
2021-07-19 22:54:26 +08:00
|
|
|
//
|