maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/clang/test/Driver/hip-toolchain-mllvm.hip

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

27 lines
902 B
Plaintext
Raw Normal View History

[HIP-Clang] propagate -mllvm options to opt and llc Change the HIP Toolchain to pass the OPT_mllvm options into OPT and LLC stages. Added a lit test to verify the command args. Reviewers: yaxunl Differential Revision: https://reviews.llvm.org/D59316 llvm-svn: 356277
2019-03-16 01:31:51 +08:00
// REQUIRES: clang-driver
// REQUIRES: x86-registered-target
// REQUIRES: amdgpu-registered-target
// RUN: %clang -### -target x86_64-linux-gnu \
[HIP] Let clang recognize .hip extension Differential Revision: https://reviews.llvm.org/D76039
2020-03-12 10:48:12 +08:00
// RUN: --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 \
[HIP-Clang] propagate -mllvm options to opt and llc Change the HIP Toolchain to pass the OPT_mllvm options into OPT and LLC stages. Added a lit test to verify the command args. Reviewers: yaxunl Differential Revision: https://reviews.llvm.org/D59316 llvm-svn: 356277
2019-03-16 01:31:51 +08:00
// RUN: -mllvm -amdgpu-function-calls=0 \
// RUN: %s 2>&1 | FileCheck %s
// CHECK: [[CLANG:".*clang.*"]] "-cc1" "-triple" "amdgcn-amd-amdhsa"
Move options to separate checks that do not need to immediately follow the previous option. NFCI llvm-svn: 356507
2019-03-20 03:34:15 +08:00
// CHECK-SAME: "-aux-triple" "x86_64-unknown-linux-gnu"
[HIP] Do not call opt/llc for -fno-gpu-rdc Currently HIP toolchain calls clang to emit bitcode then calls opt/llc for device compilation for the default -fno-gpu-rdc case, which is unnecessary since clang is able to compile a single source file to ISA. This patch fixes the HIP action builder and toolchain so that the default -fno-gpu-rdc can be done like a canonical toolchain, i.e. one clang -cc1 invocation to compile source code to ISA. This can avoid unnecessary processes to speed up the compilation, and avoid redundant LLVM passes which are performed in clang -cc1 and opt. Differential Revision: https://reviews.llvm.org/D81627
2020-06-10 03:02:53 +08:00
// CHECK-SAME: "-emit-obj"
[HIP-Clang] propagate -mllvm options to opt and llc Change the HIP Toolchain to pass the OPT_mllvm options into OPT and LLC stages. Added a lit test to verify the command args. Reviewers: yaxunl Differential Revision: https://reviews.llvm.org/D59316 llvm-svn: 356277
2019-03-16 01:31:51 +08:00
// CHECK-SAME: {{.*}} "-target-cpu" "gfx803"
// CHECK-SAME: {{.*}} "-mllvm" "-amdgpu-function-calls=0" {{.*}}
[HIP] Do not call opt/llc for -fno-gpu-rdc Currently HIP toolchain calls clang to emit bitcode then calls opt/llc for device compilation for the default -fno-gpu-rdc case, which is unnecessary since clang is able to compile a single source file to ISA. This patch fixes the HIP action builder and toolchain so that the default -fno-gpu-rdc can be done like a canonical toolchain, i.e. one clang -cc1 invocation to compile source code to ISA. This can avoid unnecessary processes to speed up the compilation, and avoid redundant LLVM passes which are performed in clang -cc1 and opt. Differential Revision: https://reviews.llvm.org/D81627
2020-06-10 03:02:53 +08:00
// CHECK-NOT: {{".*opt"}}
// CHECK-NOT: {{".*llc"}}
[HIP-Clang] propagate -mllvm options to opt and llc Change the HIP Toolchain to pass the OPT_mllvm options into OPT and LLC stages. Added a lit test to verify the command args. Reviewers: yaxunl Differential Revision: https://reviews.llvm.org/D59316 llvm-svn: 356277
2019-03-16 01:31:51 +08:00
// CHECK: [[CLANG]] "-cc1" "-triple" "amdgcn-amd-amdhsa"
Move options to separate checks that do not need to immediately follow the previous option. NFCI llvm-svn: 356507
2019-03-20 03:34:15 +08:00
// CHECK-SAME: "-aux-triple" "x86_64-unknown-linux-gnu"
[HIP] Do not call opt/llc for -fno-gpu-rdc Currently HIP toolchain calls clang to emit bitcode then calls opt/llc for device compilation for the default -fno-gpu-rdc case, which is unnecessary since clang is able to compile a single source file to ISA. This patch fixes the HIP action builder and toolchain so that the default -fno-gpu-rdc can be done like a canonical toolchain, i.e. one clang -cc1 invocation to compile source code to ISA. This can avoid unnecessary processes to speed up the compilation, and avoid redundant LLVM passes which are performed in clang -cc1 and opt. Differential Revision: https://reviews.llvm.org/D81627
2020-06-10 03:02:53 +08:00
// CHECK-SAME: "-emit-obj"
[HIP-Clang] propagate -mllvm options to opt and llc Change the HIP Toolchain to pass the OPT_mllvm options into OPT and LLC stages. Added a lit test to verify the command args. Reviewers: yaxunl Differential Revision: https://reviews.llvm.org/D59316 llvm-svn: 356277
2019-03-16 01:31:51 +08:00
// CHECK-SAME: {{.*}} "-target-cpu" "gfx900"
// CHECK-SAME: {{.*}} "-mllvm" "-amdgpu-function-calls=0" {{.*}}
[HIP] Do not call opt/llc for -fno-gpu-rdc Currently HIP toolchain calls clang to emit bitcode then calls opt/llc for device compilation for the default -fno-gpu-rdc case, which is unnecessary since clang is able to compile a single source file to ISA. This patch fixes the HIP action builder and toolchain so that the default -fno-gpu-rdc can be done like a canonical toolchain, i.e. one clang -cc1 invocation to compile source code to ISA. This can avoid unnecessary processes to speed up the compilation, and avoid redundant LLVM passes which are performed in clang -cc1 and opt. Differential Revision: https://reviews.llvm.org/D81627
2020-06-10 03:02:53 +08:00
// CHECK-NOT: {{".*opt"}}
// CHECK-NOT: {{".*llc"}}