maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/ARM/cortex-a57-misched-alu.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

85 lines
2.4 KiB
LLVM
Raw Normal View History

[ARM] Cortex-A57 scheduling model for ARM backend (AArch32) This patch implements the Cortex-A57 scheduling model. The main code is in ARMScheduleA57.td, ARMScheduleA57WriteRes.td. Small changes in cpp,.h files to support required scheduling predicates. Scheduling model implemented according to: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf. Patch by : Andrew Zhogin (submitted on his behalf, as requested). Rewiewed by: Renato Golin, Diana Picus, Javed Absar, Kristof Beyls. Differential Revision: https://reviews.llvm.org/D28152 llvm-svn: 304530
2017-06-02 16:53:19 +08:00
; REQUIRES: asserts
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
[ARM] Use post-RA MI scheduler when +use-misched is set Differential revision: https://reviews.llvm.org/D39100 llvm-svn: 316214
2017-10-20 22:29:17 +08:00
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=+use-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=POST-MISCHED
[ARM] Cortex-A57 scheduling model for ARM backend (AArch32) This patch implements the Cortex-A57 scheduling model. The main code is in ARMScheduleA57.td, ARMScheduleA57WriteRes.td. Small changes in cpp,.h files to support required scheduling predicates. Scheduling model implemented according to: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf. Patch by : Andrew Zhogin (submitted on his behalf, as requested). Rewiewed by: Renato Golin, Diana Picus, Javed Absar, Kristof Beyls. Differential Revision: https://reviews.llvm.org/D28152 llvm-svn: 304530
2017-06-02 16:53:19 +08:00
; Check the latency for ALU shifted operand variants.
;
; CHECK: ********** MI Scheduling **********
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: foo:%bb.0 entry
[ARM] Cortex-A57 scheduling model for ARM backend (AArch32) This patch implements the Cortex-A57 scheduling model. The main code is in ARMScheduleA57.td, ARMScheduleA57WriteRes.td. Small changes in cpp,.h files to support required scheduling predicates. Scheduling model implemented according to: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf. Patch by : Andrew Zhogin (submitted on his behalf, as requested). Rewiewed by: Renato Golin, Diana Picus, Javed Absar, Kristof Beyls. Differential Revision: https://reviews.llvm.org/D28152 llvm-svn: 304530
2017-06-02 16:53:19 +08:00
; ALU, basic - 1 cyc I0/I1
; CHECK: EORrr
; CHECK: rdefs left
; CHECK-NEXT: Latency : 1
; ALU, shift by immed - 2 cyc M
; CHECK: ADDrsi
; CHECK: rdefs left
; CHECK-NEXT: Latency : 2
; ALU, shift by register, unconditional - 2 cyc M
; CHECK: RSBrsr
; CHECK: rdefs left
; CHECK-NEXT: Latency : 2
; ALU, shift by register, conditional - 2 cyc I0/I1
; CHECK: ANDrsr
; CHECK: rdefs left
; CHECK-NEXT: Latency : 2
; Checking scheduling units
; CHECK: ** ScheduleDAGMILive::schedule picking next node
; Skipping COPY
; CHECK: ** ScheduleDAGMILive::schedule picking next node
; CHECK: Scheduling
; CHECK-SAME: ANDrsr
; CHECK: Ready
; CHECK-NEXT: A57UnitI
; CHECK: ** ScheduleDAGMILive::schedule picking next node
; CHECK: Scheduling
; CHECK-SAME: CMPri
; CHECK: Ready
; CHECK-NEXT: A57UnitI
; CHECK: ** ScheduleDAGMILive::schedule picking next node
; CHECK: Scheduling
; CHECK-SAME: RSBrsr
; CHECK: Ready
; CHECK-NEXT: A57UnitM
; CHECK: ** ScheduleDAGMILive::schedule picking next node
; CHECK: Scheduling
; CHECK-SAME: ADDrsi
; CHECK: Ready
; CHECK-NEXT: A57UnitM
; CHECK: ** ScheduleDAGMILive::schedule picking next node
; CHECK: Scheduling
; CHECK-SAME: EORrr
; CHECK: Ready
; CHECK-NEXT: A57UnitI
[ARM] Use post-RA MI scheduler when +use-misched is set Differential revision: https://reviews.llvm.org/D39100 llvm-svn: 316214
2017-10-20 22:29:17 +08:00
; Check that post RA MI scheduler is invoked with +use-misched
; POST-MISCHED: Before post-MI-sched
[ARM] Cortex-A57 scheduling model for ARM backend (AArch32) This patch implements the Cortex-A57 scheduling model. The main code is in ARMScheduleA57.td, ARMScheduleA57WriteRes.td. Small changes in cpp,.h files to support required scheduling predicates. Scheduling model implemented according to: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf. Patch by : Andrew Zhogin (submitted on his behalf, as requested). Rewiewed by: Renato Golin, Diana Picus, Javed Absar, Kristof Beyls. Differential Revision: https://reviews.llvm.org/D28152 llvm-svn: 304530
2017-06-02 16:53:19 +08:00
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv8r-arm-none-eabi"
; Function Attrs: norecurse nounwind readnone
define hidden i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #0 {
entry:
%xor = xor i32 %a, %b
%xor_shl = shl i32 %xor, 2
%add = add i32 %xor_shl, %d
%add_ashr = ashr i32 %add, %a
%sub = sub i32 %add_ashr, %a
%sub_lshr_pred = lshr i32 %sub, %c
%pred = icmp sgt i32 %a, 4
%and = and i32 %sub_lshr_pred, %b
%rv = select i1 %pred, i32 %and, i32 %d
ret i32 %rv
}