forked from OSchip/llvm-project
45 lines
1.5 KiB
LLVM
45 lines
1.5 KiB
LLVM
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; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 -disable-packetizer < %s | FileCheck %s
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; Test that the early start and late start values are computed correctly
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; when a Phi depends on another Phi. In this case, they should occur in
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; the same stage.
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; CHECK-DAG: [[REG3:(r[0-9]+)]] = add([[REG1:(r[0-9]+)]],#-1)
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; CHECK-DAG: [[REG2:(r[0-9]+)]] = add([[REG1]],#-1)
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; CHECK-DAG: loop0(.LBB0_[[LOOP:.]],[[REG3]])
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; CHECK-NOT: = [[REG2]]
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: }{{[ \t]*}}:endloop
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; Function Attrs: nounwind
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define void @f0(i32 %a0, i16* nocapture %a1) #0 {
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b0:
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br i1 undef, label %b1, label %b2
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b1: ; preds = %b0
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%v0 = add nsw i32 undef, -8
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br i1 undef, label %b3, label %b2
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b2: ; preds = %b2, %b1, %b0
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%v1 = phi i32 [ %v7, %b2 ], [ undef, %b0 ], [ %v0, %b1 ]
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%v2 = phi i32 [ %v1, %b2 ], [ %a0, %b0 ], [ undef, %b1 ]
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%v3 = add nsw i32 %v2, -2
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%v4 = getelementptr inbounds i16, i16* %a1, i32 %v3
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%v5 = load i16, i16* %v4, align 2, !tbaa !0
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%v6 = getelementptr inbounds i16, i16* %a1, i32 %v1
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store i16 %v5, i16* %v6, align 2, !tbaa !0
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%v7 = add nsw i32 %v1, -1
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%v8 = icmp sgt i32 %v7, 0
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br i1 %v8, label %b2, label %b3
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b3: ; preds = %b2, %b1
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"short", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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