2016-08-20 01:54:49 +08:00
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; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
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;
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; Expand-condsets eliminates the "mux" instruction, which is what this
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; testcase is checking.
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%struct._Dnk_filet.1 = type { i16, i8, i32, i8*, i8*, i8*, i8*, i8*, i8*, i32*, [2 x i32], i8*, i8*, i8*, %struct._Mbstatet.0, i8*, [8 x i8], i8 }
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%struct._Mbstatet.0 = type { i32, i16, i16 }
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@_Stdout = external global %struct._Dnk_filet.1
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@.str = external unnamed_addr constant [23 x i8], align 8
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; Test that we don't generate a new value compare if the operands are
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; the same register.
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2017-02-10 23:33:13 +08:00
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; CHECK-NOT: cmp.eq([[REG0:(r[0-9]+)]].new,[[REG0]])
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; CHECK: cmp.eq([[REG1:(r[0-9]+)]],[[REG1]])
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2016-08-20 01:54:49 +08:00
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; Function Attrs: nounwind
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declare void @fprintf(%struct._Dnk_filet.1* nocapture, i8* nocapture readonly, ...) #1
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define void @main() #0 {
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entry:
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%0 = load i32*, i32** undef, align 4
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%1 = load i32, i32* undef, align 4
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br i1 undef, label %if.end, label %_ZNSt6vectorIbSaIbEE3endEv.exit
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_ZNSt6vectorIbSaIbEE3endEv.exit:
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%2 = icmp slt i32 %1, 0
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%sub5.i.i.i = lshr i32 %1, 5
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%add619.i.i.i = add i32 %sub5.i.i.i, -134217728
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%sub5.i.pn.i.i = select i1 %2, i32 %add619.i.i.i, i32 %sub5.i.i.i
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%storemerge2.i.i = getelementptr inbounds i32, i32* %0, i32 %sub5.i.pn.i.i
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%cmp.i.i = icmp ult i32* %storemerge2.i.i, %0
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%.mux = select i1 %cmp.i.i, i32 0, i32 1
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br i1 undef, label %_ZNSt6vectorIbSaIbEE3endEv.exit57, label %if.end
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_ZNSt6vectorIbSaIbEE3endEv.exit57:
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%3 = icmp slt i32 %1, 0
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%sub5.i.i.i44 = lshr i32 %1, 5
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%add619.i.i.i45 = add i32 %sub5.i.i.i44, -134217728
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%sub5.i.pn.i.i46 = select i1 %3, i32 %add619.i.i.i45, i32 %sub5.i.i.i44
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%storemerge2.i.i47 = getelementptr inbounds i32, i32* %0, i32 %sub5.i.pn.i.i46
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%cmp.i38 = icmp ult i32* %storemerge2.i.i47, %0
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%.reg2mem.sroa.0.sroa.0.0.load14.i.reload = select i1 %cmp.i38, i32 0, i32 1
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%cmp = icmp eq i32 %.mux, %.reg2mem.sroa.0.sroa.0.0.load14.i.reload
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br i1 %cmp, label %if.end, label %if.then
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if.then:
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call void (%struct._Dnk_filet.1*, i8*, ...) @fprintf(%struct._Dnk_filet.1* @_Stdout, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @.str, i32 0, i32 0), i32 %.mux, i32 %.reg2mem.sroa.0.sroa.0.0.load14.i.reload) #1
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unreachable
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if.end:
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br i1 undef, label %_ZNSt6vectorIbSaIbEED2Ev.exit, label %if.then.i.i.i
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if.then.i.i.i:
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unreachable
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_ZNSt6vectorIbSaIbEED2Ev.exit:
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ret void
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}
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attributes #0 = { "target-cpu"="hexagonv5" }
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attributes #1 = { nounwind "target-cpu"="hexagonv5" }
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