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llvm-project/llvm/test/CodeGen/Hexagon/memops-stack.ll

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[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
; RUN: llc -march=hexagon < %s | FileCheck %s
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
; CHECK-LABEL: test0
; CHECK: memw(r29+#{{[0-9]+}}) += #1
define void @test0() #0 {
entry:
%x = alloca i32, align 4
%0 = bitcast i32* %x to i8*
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
call void @foo(i32* nonnull %x) #3
%1 = load i32, i32* %x, align 4, !tbaa !1
%inc = add nsw i32 %1, 1
store i32 %inc, i32* %x, align 4, !tbaa !1
call void @foo(i32* nonnull %x) #3
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.end.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
ret void
}
; CHECK-LABEL: test1
; CHECK: memw(r29+#{{[0-9]+}}) -= #1
define void @test1() #0 {
entry:
%x = alloca i32, align 4
%0 = bitcast i32* %x to i8*
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
call void @foo(i32* nonnull %x) #3
%1 = load i32, i32* %x, align 4, !tbaa !1
%inc = sub nsw i32 %1, 1
store i32 %inc, i32* %x, align 4, !tbaa !1
call void @foo(i32* nonnull %x) #3
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.end.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
ret void
}
; CHECK-LABEL: test2
; CHECK: memw(r29+#{{[0-9]+}}) = setbit(#0)
define void @test2() #0 {
entry:
%x = alloca i32, align 4
%0 = bitcast i32* %x to i8*
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
call void @foo(i32* nonnull %x) #3
%1 = load i32, i32* %x, align 4, !tbaa !1
%inc = or i32 %1, 1
store i32 %inc, i32* %x, align 4, !tbaa !1
call void @foo(i32* nonnull %x) #3
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.end.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
ret void
}
; CHECK-LABEL: test3
; CHECK: memw(r29+#{{[0-9]+}}) = clrbit(#0)
define void @test3() #0 {
entry:
%x = alloca i32, align 4
%0 = bitcast i32* %x to i8*
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
call void @foo(i32* nonnull %x) #3
%1 = load i32, i32* %x, align 4, !tbaa !1
%inc = and i32 %1, -2
store i32 %inc, i32* %x, align 4, !tbaa !1
call void @foo(i32* nonnull %x) #3
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.end.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
ret void
}
; CHECK-LABEL: test4
; CHECK: memw(r29+#{{[0-9]+}}) += r
define void @test4(i32 %a) #0 {
entry:
%x = alloca i32, align 4
%0 = bitcast i32* %x to i8*
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
call void @foo(i32* nonnull %x) #3
%1 = load i32, i32* %x, align 4, !tbaa !1
%inc = add nsw i32 %1, %a
store i32 %inc, i32* %x, align 4, !tbaa !1
call void @foo(i32* nonnull %x) #3
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.end.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
ret void
}
; CHECK-LABEL: test5
; CHECK: memw(r29+#{{[0-9]+}}) -= r
define void @test5(i32 %a) #0 {
entry:
%x = alloca i32, align 4
%0 = bitcast i32* %x to i8*
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
call void @foo(i32* nonnull %x) #3
%1 = load i32, i32* %x, align 4, !tbaa !1
%inc = sub nsw i32 %1, %a
store i32 %inc, i32* %x, align 4, !tbaa !1
call void @foo(i32* nonnull %x) #3
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.end.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
ret void
}
; CHECK-LABEL: test6
; CHECK: memw(r29+#{{[0-9]+}}) |= r
define void @test6(i32 %a) #0 {
entry:
%x = alloca i32, align 4
%0 = bitcast i32* %x to i8*
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
call void @foo(i32* nonnull %x) #3
%1 = load i32, i32* %x, align 4, !tbaa !1
%inc = or i32 %1, %a
store i32 %inc, i32* %x, align 4, !tbaa !1
call void @foo(i32* nonnull %x) #3
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.end.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
ret void
}
; CHECK-LABEL: test7
; CHECK: memw(r29+#{{[0-9]+}}) &= r
define void @test7(i32 %a) #0 {
entry:
%x = alloca i32, align 4
%0 = bitcast i32* %x to i8*
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
call void @foo(i32* nonnull %x) #3
%1 = load i32, i32* %x, align 4, !tbaa !1
%inc = and i32 %1, %a
store i32 %inc, i32* %x, align 4, !tbaa !1
call void @foo(i32* nonnull %x) #3
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
call void @llvm.lifetime.end.p0i8(i64 4, i8* %0) #3
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
ret void
}
declare void @foo(i32*) #2
Add address space mangling to lifetime intrinsics In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
2017-04-11 04:18:21 +08:00
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
[Hexagon] New HVX target features. This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101
2017-10-19 02:07:07 +08:00
attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
attributes #1 = { argmemonly nounwind }
[Hexagon] New HVX target features. This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101
2017-10-19 02:07:07 +08:00
attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
[Hexagon] Improve patterns with stack-based addressing - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
2016-07-15 23:35:52 +08:00
attributes #3 = { nounwind }
!1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"}