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llvm-project/llvm/test/CodeGen/AArch64/sub1.ll

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[AArch64] add test to show sub-optimal isel; NFC llvm-svn: 324404
2018-02-07 05:25:02 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
define i64 @sub1_disguised_constant(i64 %x) {
; CHECK-LABEL: sub1_disguised_constant:
; CHECK: // %bb.0:
[TargetLowering] try to create -1 constant operand for math ops via demanded bits This reverses instcombine's demanded bits' transform which always tries to clear bits in constants. As noted in PR35792 and shown in the test diffs: https://bugs.llvm.org/show_bug.cgi?id=35792 ...we can do better in codegen by trying to form -1. The x86 sub test shows a missed opportunity. I did investigate changing instcombine's behavior, but it would be more work to change canonicalization in IR. Clearing bits / shrinking constants can allow killing instructions, so we'd have to figure out how to not regress those cases. Differential Revision: https://reviews.llvm.org/D42986 llvm-svn: 324839
2018-02-11 22:38:23 +08:00
; CHECK-NEXT: sub w8, w0, #1 // =1
[AArch64] add test to show sub-optimal isel; NFC llvm-svn: 324404
2018-02-07 05:25:02 +08:00
; CHECK-NEXT: and w8, w0, w8
; CHECK-NEXT: and x0, x8, #0xffff
; CHECK-NEXT: ret
%a1 = and i64 %x, 65535
%a2 = add i64 %x, 65535
%r = and i64 %a1, %a2
ret i64 %r
}