2018-12-18 01:38:11 +08:00
..
***** ***** ***** ***** ***** ***** ***** ***** ***** *****
* *
* Automatically generated file, do not edit! *
* *
***** ***** ***** ***** ***** ***** ***** ***** ***** *****
2021-07-23 17:51:37 +08:00
.. _amdgpu_synid_gfx9_hwreg:
2018-12-18 01:38:11 +08:00
hwreg
2021-07-23 17:51:37 +08:00
=====
2018-12-18 01:38:11 +08:00
Bits of a hardware register being accessed.
The bits of this operand have the following meaning:
2019-09-25 20:38:35 +08:00
======= ===================== ============
Bits Description Value Range
======= ===================== ============
5:0 Register *id* . 0..63
10:6 First bit *offset* . 0..31
15:11 *Size* in bits. 1..32
======= ===================== ============
2018-12-18 01:38:11 +08:00
2019-09-25 20:38:35 +08:00
This operand may be specified as one of the following:
* An :ref: `integer_number<amdgpu_synid_integer_number>` or an :ref: `absolute_expression<amdgpu_synid_absolute_expression>` . The value must be in the range 0..0xFFFF.
* An *hwreg* value described below.
2018-12-18 01:38:11 +08:00
==================================== ============================================================================
2019-09-25 20:38:35 +08:00
Hwreg Value Syntax Description
2018-12-18 01:38:11 +08:00
==================================== ============================================================================
hwreg({0..63}) All bits of a register indicated by its *id* .
hwreg(<*name* >) All bits of a register indicated by its *name* .
hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id* , first bit *offset* and *size* .
hwreg(<*name* >, {0..31}, {1..32}) Register bits indicated by register *name* , first bit *offset* and *size* .
==================================== ============================================================================
2019-09-25 20:38:35 +08:00
Numeric values may be specified as positive :ref: `integer numbers<amdgpu_synid_integer_number>`
or :ref: `absolute expressions<amdgpu_synid_absolute_expression>` .
2018-12-18 01:38:11 +08:00
Defined register *names* include:
=================== ==========================================
Name Description
=================== ==========================================
HW_REG_MODE Shader writeable mode bits.
HW_REG_STATUS Shader read-only status.
HW_REG_TRAPSTS Trap status.
HW_REG_HW_ID Id of wave, simd, compute unit, etc.
HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
HW_REG_LDS_ALLOC Per-wave LDS allocation.
HW_REG_IB_STS Counters of outstanding instructions.
HW_REG_SH_MEM_BASES Memory aperture.
2022-02-04 22:55:01 +08:00
HW_REG_TBA_LO tba_lo register.
HW_REG_TBA_HI tba_hi register.
HW_REG_TMA_LO tma_lo register.
HW_REG_TMA_HI tma_hi register.
2018-12-18 01:38:11 +08:00
=================== ==========================================
Examples:
2018-12-18 02:53:10 +08:00
.. parsed-literal ::
2018-12-18 01:38:11 +08:00
2019-09-25 20:38:35 +08:00
reg = 1
offset = 2
size = 4
hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
s_getreg_b32 s2, 0x1881
s_getreg_b32 s2, hwreg_enc // the same as above
s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
2018-12-18 01:38:11 +08:00
s_getreg_b32 s2, hwreg(15)
s_getreg_b32 s2, hwreg(51, 1, 31)
s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)