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llvm-project/llvm/docs/AMDGPU/gfx8_label.rst

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[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-18 01:38:11 +08:00
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[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types.
2021-08-27 22:16:22 +08:00
.. _amdgpu_synid_gfx8_label:
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-18 01:38:11 +08:00
label
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types.
2021-08-27 22:16:22 +08:00
=====
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-18 01:38:11 +08:00
A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
[AMDGPU][MC][DOC] Updated AMD GPU assembler description. Summary of changes: - Updated to reflect recent changes in assembler; - Minor bugfixing and improvements. llvm-svn: 372857
2019-09-25 20:38:35 +08:00
This operand may be specified as one of the following:
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-18 01:38:11 +08:00
[AMDGPU][MC][DOC] Updated AMD GPU assembler description. Summary of changes: - Updated to reflect recent changes in assembler; - Minor bugfixing and improvements. llvm-svn: 372857
2019-09-25 20:38:35 +08:00
* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-18 01:38:11 +08:00
Examples:
[AMDGPU][MC][DOC] A fix for build failure in r349370 llvm-svn: 349375
2018-12-18 02:53:10 +08:00
.. parsed-literal::
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-18 01:38:11 +08:00
offset = 30
[AMDGPU][MC][DOC] Updated AMD GPU assembler description. Summary of changes: - Updated to reflect recent changes in assembler; - Minor bugfixing and improvements. llvm-svn: 372857
2019-09-25 20:38:35 +08:00
label_1:
label_2 = . + 4
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-18 01:38:11 +08:00
s_branch 32
[AMDGPU][MC][DOC] Updated AMD GPU assembler description. Summary of changes: - Updated to reflect recent changes in assembler; - Minor bugfixing and improvements. llvm-svn: 372857
2019-09-25 20:38:35 +08:00
s_branch offset + 2
s_branch label_1
s_branch label_2
s_branch label_3
s_branch label_4
label_3 = label_2 + 4
label_4: