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llvm-project/clang/test/Driver/riscv-abi.c

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[RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
2018-01-11 21:36:56 +08:00
// RUN: %clang -target riscv32-unknown-elf %s -### -o %t.o 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
// RUN: %clang -target riscv32-unknown-elf %s -### -o %t.o -mabi=ilp32 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
[RISCV] Pass -target-abi to -cc1as The RISC-V assembler needs the target ABI because it defines a flag of the ELF file, as described in [1]. Make clang (the driver) to pass the target ABI to -cc1as in exactly the same way it does for -cc1. Currently -cc1as knows about -target-abi but is not handling it. Handle it and pass it to the MC layer via MCTargetOptions. [1] https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#file-header Differential Revision: https://reviews.llvm.org/D59298 llvm-svn: 356981
2019-03-26 16:01:18 +08:00
// RUN: %clang -target riscv32-unknown-elf -x assembler %s -### -o %t.o 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
// RUN: %clang -target riscv32-unknown-elf -x assembler %s -### -o %t.o \
// RUN: -mabi=ilp32 2>&1 | FileCheck -check-prefix=CHECK-ILP32 %s
[RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
2018-01-11 21:36:56 +08:00
// CHECK-ILP32: "-target-abi" "ilp32"
[RISCV] Hard float ABI support The RISC-V hard float calling convention requires the frontend to: * Detect cases where, once "flattened", a struct can be passed using int+fp or fp+fp registers under the hard float ABI and coerce to the appropriate type(s) * Track usage of GPRs and FPRs in order to gate the above, and to determine when signext/zeroext attributes must be added to integer scalars This patch attempts to do this in compliance with the documented ABI, and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as author of that code I've tagged you as reviewer for initial feedback on my usage. Note that a previous version of the ABI indicated that when passing an int+fp struct using a GPR+FPR, the int would need to be sign or zero-extended appropriately. GCC never did this and the ABI was changed, which makes life easier as ABIArgInfo::CoerceAndExpand can't currently handle sign/zero-extension attributes. Re-landed after backing out 366450 due to missed hunks. Differential Revision: https://reviews.llvm.org/D60456 llvm-svn: 366480
2019-07-19 02:29:59 +08:00
// RUN: %clang -target riscv32-unknown-elf %s -### -o %t.o -march=rv32if -mabi=ilp32f 2>&1 \
[RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
2018-01-11 21:36:56 +08:00
// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s
[RISCV] Hard float ABI support The RISC-V hard float calling convention requires the frontend to: * Detect cases where, once "flattened", a struct can be passed using int+fp or fp+fp registers under the hard float ABI and coerce to the appropriate type(s) * Track usage of GPRs and FPRs in order to gate the above, and to determine when signext/zeroext attributes must be added to integer scalars This patch attempts to do this in compliance with the documented ABI, and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as author of that code I've tagged you as reviewer for initial feedback on my usage. Note that a previous version of the ABI indicated that when passing an int+fp struct using a GPR+FPR, the int would need to be sign or zero-extended appropriately. GCC never did this and the ABI was changed, which makes life easier as ABIArgInfo::CoerceAndExpand can't currently handle sign/zero-extension attributes. Re-landed after backing out 366450 due to missed hunks. Differential Revision: https://reviews.llvm.org/D60456 llvm-svn: 366480
2019-07-19 02:29:59 +08:00
// CHECK-ILP32F: "-target-abi" "ilp32f"
[RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
2018-01-11 21:36:56 +08:00
[RISCV] Hard float ABI support The RISC-V hard float calling convention requires the frontend to: * Detect cases where, once "flattened", a struct can be passed using int+fp or fp+fp registers under the hard float ABI and coerce to the appropriate type(s) * Track usage of GPRs and FPRs in order to gate the above, and to determine when signext/zeroext attributes must be added to integer scalars This patch attempts to do this in compliance with the documented ABI, and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as author of that code I've tagged you as reviewer for initial feedback on my usage. Note that a previous version of the ABI indicated that when passing an int+fp struct using a GPR+FPR, the int would need to be sign or zero-extended appropriately. GCC never did this and the ABI was changed, which makes life easier as ABIArgInfo::CoerceAndExpand can't currently handle sign/zero-extension attributes. Re-landed after backing out 366450 due to missed hunks. Differential Revision: https://reviews.llvm.org/D60456 llvm-svn: 366480
2019-07-19 02:29:59 +08:00
// RUN: %clang -target riscv32-unknown-elf %s -### -o %t.o -march=rv32ifd -mabi=ilp32d 2>&1 \
[RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
2018-01-11 21:36:56 +08:00
// RUN: | FileCheck -check-prefix=CHECK-ILP32D %s
[RISCV] Match GCC `-march`/`-mabi` driver defaults Summary: Clang/LLVM is a cross-compiler, and so we don't have to make a choice about `-march`/`-mabi` at build-time, but we may have to compute a default `-march`/`-mabi` when compiling a program. Until now, each place that has needed a default `-march` has calculated one itself. This patch adds a single place where a default `-march` is calculated, in order to avoid calculating different defaults in different places. This patch adds a new function `riscv::getRISCVArch` which encapsulates this logic based on GCC's for computing a default `-march` value when none is provided. This patch also updates the logic in `riscv::getRISCVABI` to match the logic in GCC's build system for computing a default `-mabi`. This patch also updates anywhere that `-march` is used to now use the new function which can compute a default. In particular, we now explicitly pass a `-march` value down to the gnu assembler. GCC has convoluted logic in its build system to choose a default `-march`/`-mabi` based on build options, which would be good to match. This patch is based on the logic in GCC 9.2.0. This commit's logic is different to GCC's only for baremetal targets, where we default to rv32imac/ilp32 or rv64imac/lp64 depending on the target triple. Tests have been updated to match the new logic. Reviewers: asb, luismarques, rogfer01, kito-cheng, khchen Reviewed By: asb, luismarques Subscribers: sameer.abuasal, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D69383
2019-11-15 23:10:02 +08:00
// RUN: %clang -target riscv32-unknown-linux-gnu %s -### -o %t.o 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32D %s
// RUN: %clang -target riscv32-unknown-linux-gnu -x assembler %s -### -o %t.o 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32D %s
[RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
2018-01-11 21:36:56 +08:00
[RISCV] Hard float ABI support The RISC-V hard float calling convention requires the frontend to: * Detect cases where, once "flattened", a struct can be passed using int+fp or fp+fp registers under the hard float ABI and coerce to the appropriate type(s) * Track usage of GPRs and FPRs in order to gate the above, and to determine when signext/zeroext attributes must be added to integer scalars This patch attempts to do this in compliance with the documented ABI, and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as author of that code I've tagged you as reviewer for initial feedback on my usage. Note that a previous version of the ABI indicated that when passing an int+fp struct using a GPR+FPR, the int would need to be sign or zero-extended appropriately. GCC never did this and the ABI was changed, which makes life easier as ABIArgInfo::CoerceAndExpand can't currently handle sign/zero-extension attributes. Re-landed after backing out 366450 due to missed hunks. Differential Revision: https://reviews.llvm.org/D60456 llvm-svn: 366480
2019-07-19 02:29:59 +08:00
// CHECK-ILP32D: "-target-abi" "ilp32d"
[RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
2018-01-11 21:36:56 +08:00
// RUN: not %clang -target riscv32-unknown-elf %s -o %t.o -mabi=lp64 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-RV32-LP64 %s
// CHECK-RV32-LP64: error: unknown target ABI 'lp64'
// RUN: %clang -target riscv64-unknown-elf %s -### -o %t.o 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
// RUN: %clang -target riscv64-unknown-elf %s -### -o %t.o -mabi=lp64 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
[RISCV] Pass -target-abi to -cc1as The RISC-V assembler needs the target ABI because it defines a flag of the ELF file, as described in [1]. Make clang (the driver) to pass the target ABI to -cc1as in exactly the same way it does for -cc1. Currently -cc1as knows about -target-abi but is not handling it. Handle it and pass it to the MC layer via MCTargetOptions. [1] https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#file-header Differential Revision: https://reviews.llvm.org/D59298 llvm-svn: 356981
2019-03-26 16:01:18 +08:00
// RUN: %clang -target riscv64-unknown-elf -x assembler %s -### -o %t.o 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
// RUN: %clang -target riscv64-unknown-elf -x assembler %s -### -o %t.o \
// RUN: -mabi=lp64 2>&1 | FileCheck -check-prefix=CHECK-LP64 %s
[RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
2018-01-11 21:36:56 +08:00
// CHECK-LP64: "-target-abi" "lp64"
[RISCV] Hard float ABI support The RISC-V hard float calling convention requires the frontend to: * Detect cases where, once "flattened", a struct can be passed using int+fp or fp+fp registers under the hard float ABI and coerce to the appropriate type(s) * Track usage of GPRs and FPRs in order to gate the above, and to determine when signext/zeroext attributes must be added to integer scalars This patch attempts to do this in compliance with the documented ABI, and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as author of that code I've tagged you as reviewer for initial feedback on my usage. Note that a previous version of the ABI indicated that when passing an int+fp struct using a GPR+FPR, the int would need to be sign or zero-extended appropriately. GCC never did this and the ABI was changed, which makes life easier as ABIArgInfo::CoerceAndExpand can't currently handle sign/zero-extension attributes. Re-landed after backing out 366450 due to missed hunks. Differential Revision: https://reviews.llvm.org/D60456 llvm-svn: 366480
2019-07-19 02:29:59 +08:00
// RUN: %clang -target riscv64-unknown-elf %s -### -o %t.o -march=rv64f -mabi=lp64f 2>&1 \
[RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
2018-01-11 21:36:56 +08:00
// RUN: | FileCheck -check-prefix=CHECK-LP64F %s
[RISCV] Hard float ABI support The RISC-V hard float calling convention requires the frontend to: * Detect cases where, once "flattened", a struct can be passed using int+fp or fp+fp registers under the hard float ABI and coerce to the appropriate type(s) * Track usage of GPRs and FPRs in order to gate the above, and to determine when signext/zeroext attributes must be added to integer scalars This patch attempts to do this in compliance with the documented ABI, and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as author of that code I've tagged you as reviewer for initial feedback on my usage. Note that a previous version of the ABI indicated that when passing an int+fp struct using a GPR+FPR, the int would need to be sign or zero-extended appropriately. GCC never did this and the ABI was changed, which makes life easier as ABIArgInfo::CoerceAndExpand can't currently handle sign/zero-extension attributes. Re-landed after backing out 366450 due to missed hunks. Differential Revision: https://reviews.llvm.org/D60456 llvm-svn: 366480
2019-07-19 02:29:59 +08:00
// CHECK-LP64F: "-target-abi" "lp64f"
[RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
2018-01-11 21:36:56 +08:00
[RISCV] Hard float ABI support The RISC-V hard float calling convention requires the frontend to: * Detect cases where, once "flattened", a struct can be passed using int+fp or fp+fp registers under the hard float ABI and coerce to the appropriate type(s) * Track usage of GPRs and FPRs in order to gate the above, and to determine when signext/zeroext attributes must be added to integer scalars This patch attempts to do this in compliance with the documented ABI, and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as author of that code I've tagged you as reviewer for initial feedback on my usage. Note that a previous version of the ABI indicated that when passing an int+fp struct using a GPR+FPR, the int would need to be sign or zero-extended appropriately. GCC never did this and the ABI was changed, which makes life easier as ABIArgInfo::CoerceAndExpand can't currently handle sign/zero-extension attributes. Re-landed after backing out 366450 due to missed hunks. Differential Revision: https://reviews.llvm.org/D60456 llvm-svn: 366480
2019-07-19 02:29:59 +08:00
// RUN: %clang -target riscv64-unknown-elf %s -### -o %t.o -march=rv64d -mabi=lp64d 2>&1 \
[RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
2018-01-11 21:36:56 +08:00
// RUN: | FileCheck -check-prefix=CHECK-LP64D %s
[RISCV] Match GCC `-march`/`-mabi` driver defaults Summary: Clang/LLVM is a cross-compiler, and so we don't have to make a choice about `-march`/`-mabi` at build-time, but we may have to compute a default `-march`/`-mabi` when compiling a program. Until now, each place that has needed a default `-march` has calculated one itself. This patch adds a single place where a default `-march` is calculated, in order to avoid calculating different defaults in different places. This patch adds a new function `riscv::getRISCVArch` which encapsulates this logic based on GCC's for computing a default `-march` value when none is provided. This patch also updates the logic in `riscv::getRISCVABI` to match the logic in GCC's build system for computing a default `-mabi`. This patch also updates anywhere that `-march` is used to now use the new function which can compute a default. In particular, we now explicitly pass a `-march` value down to the gnu assembler. GCC has convoluted logic in its build system to choose a default `-march`/`-mabi` based on build options, which would be good to match. This patch is based on the logic in GCC 9.2.0. This commit's logic is different to GCC's only for baremetal targets, where we default to rv32imac/ilp32 or rv64imac/lp64 depending on the target triple. Tests have been updated to match the new logic. Reviewers: asb, luismarques, rogfer01, kito-cheng, khchen Reviewed By: asb, luismarques Subscribers: sameer.abuasal, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D69383
2019-11-15 23:10:02 +08:00
// RUN: %clang -target riscv64-unknown-linux-gnu %s -### -o %t.o 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64D %s
// RUN: %clang -target riscv64-unknown-linux-gnu -x assembler %s -### -o %t.o 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64D %s
[RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
2018-01-11 21:36:56 +08:00
[RISCV] Hard float ABI support The RISC-V hard float calling convention requires the frontend to: * Detect cases where, once "flattened", a struct can be passed using int+fp or fp+fp registers under the hard float ABI and coerce to the appropriate type(s) * Track usage of GPRs and FPRs in order to gate the above, and to determine when signext/zeroext attributes must be added to integer scalars This patch attempts to do this in compliance with the documented ABI, and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as author of that code I've tagged you as reviewer for initial feedback on my usage. Note that a previous version of the ABI indicated that when passing an int+fp struct using a GPR+FPR, the int would need to be sign or zero-extended appropriately. GCC never did this and the ABI was changed, which makes life easier as ABIArgInfo::CoerceAndExpand can't currently handle sign/zero-extension attributes. Re-landed after backing out 366450 due to missed hunks. Differential Revision: https://reviews.llvm.org/D60456 llvm-svn: 366480
2019-07-19 02:29:59 +08:00
// CHECK-LP64D: "-target-abi" "lp64d"
[RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
2018-01-11 21:36:56 +08:00
// RUN: not %clang -target riscv64-unknown-elf %s -o %t.o -mabi=ilp32 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-RV64-ILP32 %s
// CHECK-RV64-ILP32: error: unknown target ABI 'ilp32'