2012-12-12 05:25:42 +08:00
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//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition of the TargetLowering class that is common
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/// to all AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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2016-03-11 16:00:27 +08:00
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
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2012-12-12 05:25:42 +08:00
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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2013-06-28 23:47:08 +08:00
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class AMDGPUMachineFunction;
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2014-02-25 05:01:28 +08:00
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class AMDGPUSubtarget;
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2012-12-12 05:25:42 +08:00
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class MachineRegisterInfo;
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class AMDGPUTargetLowering : public TargetLowering {
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2016-11-02 01:49:33 +08:00
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private:
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/// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
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/// legalized from a smaller type VT. Need to match pre-legalized type because
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/// the generic legalization inserts the add/sub between the select and
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/// compare.
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SDValue getFFBH_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL) const;
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2014-02-25 05:01:28 +08:00
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protected:
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const AMDGPUSubtarget *Subtarget;
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2013-08-15 07:25:00 +08:00
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SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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2012-12-12 05:25:42 +08:00
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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2013-08-26 23:05:44 +08:00
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/// \brief Split a vector store into multiple scalar stores.
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2014-04-18 15:40:20 +08:00
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/// \returns The resulting chain.
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2014-06-16 04:08:02 +08:00
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2014-09-11 05:44:27 +08:00
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SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
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2014-06-19 01:05:30 +08:00
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SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
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2014-06-19 01:05:26 +08:00
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SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
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2014-06-19 06:03:45 +08:00
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SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
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2015-01-22 02:18:25 +08:00
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SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
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2014-06-19 01:05:30 +08:00
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SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
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2016-01-12 00:50:29 +08:00
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SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
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2016-01-12 06:01:48 +08:00
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SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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2014-10-04 07:54:41 +08:00
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SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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2013-10-31 01:22:05 +08:00
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SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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2014-10-04 07:54:41 +08:00
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SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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2012-12-12 05:25:42 +08:00
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2014-10-04 07:54:56 +08:00
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SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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2016-11-02 00:31:48 +08:00
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SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
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2014-10-04 07:54:56 +08:00
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SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
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2014-06-16 04:23:38 +08:00
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SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
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2016-01-19 06:01:13 +08:00
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protected:
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2016-07-02 06:55:55 +08:00
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bool shouldCombineMemoryType(EVT VT) const;
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2016-07-02 06:47:50 +08:00
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SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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2014-07-15 10:06:31 +08:00
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SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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2017-02-22 07:35:48 +08:00
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SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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2016-09-14 23:19:03 +08:00
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SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
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unsigned Opc, SDValue LHS,
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uint32_t ValLo, uint32_t ValHi) const;
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2015-07-15 02:20:33 +08:00
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SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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2016-01-19 06:01:13 +08:00
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SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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2016-01-19 05:43:36 +08:00
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SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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2014-07-01 01:55:48 +08:00
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SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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2016-08-27 09:32:27 +08:00
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SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
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2016-06-12 23:39:02 +08:00
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SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
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SDValue RHS, DAGCombinerInfo &DCI) const;
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2016-01-12 01:02:00 +08:00
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SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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2017-01-12 08:09:34 +08:00
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SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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2017-02-02 10:27:04 +08:00
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SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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2014-07-01 01:55:48 +08:00
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2014-06-11 11:29:54 +08:00
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static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
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2012-12-12 05:25:42 +08:00
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2014-07-21 22:01:14 +08:00
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virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
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SelectionDAG &DAG) const;
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2014-07-25 01:10:35 +08:00
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2016-01-19 06:01:13 +08:00
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/// Return 64-bit value Op as two 32-bit integers.
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std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
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SelectionDAG &DAG) const;
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2016-01-19 06:09:04 +08:00
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SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
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SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
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2016-01-19 06:01:13 +08:00
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2014-07-25 01:10:35 +08:00
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/// \brief Split a vector load into 2 loads of half the vector.
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SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
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/// \brief Split a vector store into 2 stores of half the vector.
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2013-10-23 08:44:32 +08:00
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SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
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2014-07-25 01:10:35 +08:00
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2013-08-26 23:05:44 +08:00
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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2014-06-23 05:43:01 +08:00
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SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
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2015-01-23 07:42:43 +08:00
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SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
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2014-08-13 01:31:20 +08:00
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SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
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2014-11-15 09:07:53 +08:00
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void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &Results) const;
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2016-09-17 05:53:00 +08:00
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void analyzeFormalArgumentsCompute(CCState &State,
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const SmallVectorImpl<ISD::InputArg> &Ins) const;
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2013-03-07 17:03:52 +08:00
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void AnalyzeFormalArguments(CCState &State,
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const SmallVectorImpl<ISD::InputArg> &Ins) const;
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2016-01-14 01:23:04 +08:00
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void AnalyzeReturn(CCState &State,
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const SmallVectorImpl<ISD::OutputArg> &Outs) const;
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2013-03-07 17:03:52 +08:00
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2012-12-12 05:25:42 +08:00
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public:
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2016-06-24 14:30:11 +08:00
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AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
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2012-12-12 05:25:42 +08:00
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2017-01-19 14:35:27 +08:00
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bool mayIgnoreSignedZero(SDValue Op) const {
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2017-01-25 14:27:02 +08:00
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if (getTargetMachine().Options.NoSignedZerosFPMath)
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2017-01-19 14:35:27 +08:00
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return true;
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if (const auto *BO = dyn_cast<BinaryWithFlagsSDNode>(Op))
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return BO->Flags.hasNoSignedZeros();
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return false;
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}
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2014-04-29 15:57:24 +08:00
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bool isFAbsFree(EVT VT) const override;
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bool isFNegFree(EVT VT) const override;
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bool isTruncateFree(EVT Src, EVT Dest) const override;
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bool isTruncateFree(Type *Src, Type *Dest) const override;
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bool isZExtFree(Type *Src, Type *Dest) const override;
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bool isZExtFree(EVT Src, EVT Dest) const override;
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2014-06-26 21:45:47 +08:00
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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2014-04-29 15:57:24 +08:00
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bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
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2015-07-09 10:09:04 +08:00
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MVT getVectorIdxTy(const DataLayout &) const override;
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2014-06-24 02:00:55 +08:00
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bool isSelectSupported(SelectSupportKind) const override;
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2014-06-16 04:23:38 +08:00
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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bool ShouldShrinkFPConstant(EVT VT) const override;
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2014-12-12 08:00:24 +08:00
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bool shouldReduceLoadWidth(SDNode *Load,
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ISD::LoadExtType ExtType,
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EVT ExtVT) const override;
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2014-06-16 04:23:38 +08:00
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2016-07-02 06:47:50 +08:00
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bool isLoadBitCastBeneficial(EVT, EVT) const final;
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2015-05-24 08:51:27 +08:00
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bool storeOfVectorConstantIsCheap(EVT MemVT,
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unsigned NumElem,
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unsigned AS) const override;
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2015-10-13 07:59:50 +08:00
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bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
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2015-01-14 03:46:48 +08:00
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bool isCheapToSpeculateCttz() const override;
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bool isCheapToSpeculateCtlz() const override;
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2016-06-12 23:39:02 +08:00
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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2014-04-29 15:57:24 +08:00
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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2016-06-12 23:39:02 +08:00
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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2014-04-29 15:57:24 +08:00
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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2015-08-27 02:37:13 +08:00
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
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SelectionDAG &DAG) const;
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2014-04-29 15:57:24 +08:00
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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2014-06-16 04:23:38 +08:00
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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2014-04-29 15:57:24 +08:00
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void ReplaceNodeResults(SDNode * N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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2014-03-28 01:23:24 +08:00
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2017-02-01 08:42:40 +08:00
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SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
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2016-06-12 23:39:02 +08:00
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SDValue RHS, SDValue True, SDValue False,
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SDValue CC, DAGCombinerInfo &DCI) const;
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2014-11-15 02:30:06 +08:00
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2014-04-29 15:57:24 +08:00
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const char* getTargetNodeName(unsigned Opcode) const override;
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2012-12-12 05:25:42 +08:00
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2016-08-04 20:47:28 +08:00
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bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
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return true;
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}
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2016-11-11 07:31:06 +08:00
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SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
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int &RefinementSteps, bool &UseOneConstNR,
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bool Reciprocal) const override;
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2016-10-21 00:55:45 +08:00
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SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
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int &RefinementSteps) const override;
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2015-01-14 04:53:18 +08:00
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2014-04-29 15:57:24 +08:00
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virtual SDNode *PostISelFolding(MachineSDNode *N,
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2016-03-11 16:00:27 +08:00
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SelectionDAG &DAG) const = 0;
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2013-02-27 01:52:16 +08:00
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2012-12-12 05:25:42 +08:00
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/// \brief Determine which of the bits specified in \p Mask are known to be
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/// either zero or one and return them in the \p KnownZero and \p KnownOne
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/// bitsets.
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2014-05-15 05:14:37 +08:00
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void computeKnownBitsForTargetNode(const SDValue Op,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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2012-12-12 05:25:42 +08:00
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2014-09-03 19:41:21 +08:00
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unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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2014-07-21 23:45:01 +08:00
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/// \brief Helper function that adds Reg to the LiveIn list of the DAG's
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/// MachineFunction.
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///
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/// \returns a RegisterSDNode representing Reg.
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virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const;
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2015-07-10 05:20:37 +08:00
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enum ImplicitParameter {
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2016-06-22 04:46:20 +08:00
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FIRST_IMPLICIT,
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GRID_DIM = FIRST_IMPLICIT,
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GRID_OFFSET,
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2015-07-10 05:20:37 +08:00
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};
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/// \brief Helper function that returns the byte offset of the given
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/// type of implicit parameter.
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2015-07-29 02:09:55 +08:00
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uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
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2015-07-10 05:20:37 +08:00
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const ImplicitParameter Param) const;
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2012-12-12 05:25:42 +08:00
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};
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namespace AMDGPUISD {
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2015-05-08 05:33:59 +08:00
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enum NodeType : unsigned {
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2012-12-12 05:25:42 +08:00
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// AMDIL ISD Opcodes
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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CALL, // Function call based on a single integer
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UMUL, // 32bit unsigned multiplication
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BRANCH_COND,
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// End AMDIL ISD Opcodes
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2016-06-23 04:15:28 +08:00
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ENDPGM,
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RETURN,
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2012-12-12 05:25:42 +08:00
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DWORDADDR,
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FRACT,
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2017-02-22 07:35:48 +08:00
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/// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
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/// modifier behavior with dx10_enable.
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2014-06-13 05:15:44 +08:00
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CLAMP,
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2017-02-22 07:35:48 +08:00
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2016-08-27 09:32:27 +08:00
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// This is SETCC with the full mask result which is used for a compare with a
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2016-07-29 00:42:13 +08:00
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// result bit per item in the wavefront.
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2016-08-27 09:32:27 +08:00
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|
|
SETCC,
|
2016-12-07 10:42:15 +08:00
|
|
|
SETREG,
|
|
|
|
// FP ops with input and output chain.
|
|
|
|
FMA_W_CHAIN,
|
|
|
|
FMUL_W_CHAIN,
|
2014-06-19 09:19:19 +08:00
|
|
|
|
|
|
|
// SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
|
|
|
|
// Denormals handled on some parts.
|
2013-07-09 23:03:11 +08:00
|
|
|
COS_HW,
|
|
|
|
SIN_HW,
|
2014-11-14 07:03:09 +08:00
|
|
|
FMAX_LEGACY,
|
|
|
|
FMIN_LEGACY,
|
2014-11-15 04:08:52 +08:00
|
|
|
FMAX3,
|
|
|
|
SMAX3,
|
|
|
|
UMAX3,
|
|
|
|
FMIN3,
|
|
|
|
SMIN3,
|
|
|
|
UMIN3,
|
2016-01-29 04:53:42 +08:00
|
|
|
FMED3,
|
|
|
|
SMED3,
|
|
|
|
UMED3,
|
2012-12-12 05:25:42 +08:00
|
|
|
URECIP,
|
2014-06-19 09:19:19 +08:00
|
|
|
DIV_SCALE,
|
|
|
|
DIV_FMAS,
|
|
|
|
DIV_FIXUP,
|
2017-02-25 07:00:29 +08:00
|
|
|
// For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
|
|
|
|
// treated as an illegal operation.
|
|
|
|
FMAD_FTZ,
|
2014-06-19 09:19:19 +08:00
|
|
|
TRIG_PREOP, // 1 ULP max error for f64
|
|
|
|
|
|
|
|
// RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
|
|
|
|
// For f64, max error 2^29 ULP, handles denormals.
|
|
|
|
RCP,
|
|
|
|
RSQ,
|
2016-07-27 00:45:45 +08:00
|
|
|
RCP_LEGACY,
|
2014-06-25 06:13:39 +08:00
|
|
|
RSQ_LEGACY,
|
2016-07-27 00:45:45 +08:00
|
|
|
FMUL_LEGACY,
|
2016-02-13 09:03:00 +08:00
|
|
|
RSQ_CLAMP,
|
2014-08-16 01:30:25 +08:00
|
|
|
LDEXP,
|
2015-01-07 07:00:37 +08:00
|
|
|
FP_CLASS,
|
2013-05-18 00:50:32 +08:00
|
|
|
DOT4,
|
2015-05-01 01:15:56 +08:00
|
|
|
CARRY,
|
|
|
|
BORROW,
|
2014-03-18 02:58:11 +08:00
|
|
|
BFE_U32, // Extract range of bits with zero extension to 32-bits.
|
|
|
|
BFE_I32, // Extract range of bits with sign extension to 32-bits.
|
2014-04-01 02:21:13 +08:00
|
|
|
BFI, // (src0 & src1) | (~src0 & src2)
|
|
|
|
BFM, // Insert a range of bits into a 32-bit word.
|
2016-01-12 01:02:00 +08:00
|
|
|
FFBH_U32, // ctlz with -1 if input is zero.
|
2016-07-19 02:35:05 +08:00
|
|
|
FFBH_I32,
|
2014-04-08 03:45:41 +08:00
|
|
|
MUL_U24,
|
|
|
|
MUL_I24,
|
2016-08-27 09:32:27 +08:00
|
|
|
MULHI_U24,
|
|
|
|
MULHI_I24,
|
2014-05-23 02:00:15 +08:00
|
|
|
MAD_U24,
|
|
|
|
MAD_I24,
|
2016-08-27 09:32:27 +08:00
|
|
|
MUL_LOHI_I24,
|
|
|
|
MUL_LOHI_U24,
|
2013-05-18 00:50:20 +08:00
|
|
|
TEXTURE_FETCH,
|
2016-12-06 04:23:10 +08:00
|
|
|
EXPORT, // exp on SI+
|
|
|
|
EXPORT_DONE, // exp on SI+ with done bit set
|
|
|
|
R600_EXPORT,
|
2013-01-23 10:09:03 +08:00
|
|
|
CONST_ADDRESS,
|
2013-02-07 01:32:29 +08:00
|
|
|
REGISTER_LOAD,
|
|
|
|
REGISTER_STORE,
|
2013-08-15 07:24:45 +08:00
|
|
|
LOAD_INPUT,
|
|
|
|
SAMPLE,
|
|
|
|
SAMPLEB,
|
|
|
|
SAMPLED,
|
|
|
|
SAMPLEL,
|
2014-06-12 01:50:44 +08:00
|
|
|
|
|
|
|
// These cvt_f32_ubyte* nodes need to remain consecutive and in order.
|
|
|
|
CVT_F32_UBYTE0,
|
|
|
|
CVT_F32_UBYTE1,
|
|
|
|
CVT_F32_UBYTE2,
|
|
|
|
CVT_F32_UBYTE3,
|
2017-02-22 08:27:34 +08:00
|
|
|
|
|
|
|
// Convert two float 32 numbers into a single register holding two packed f16
|
|
|
|
// with round to zero.
|
|
|
|
CVT_PKRTZ_F16_F32,
|
|
|
|
|
2017-03-16 03:04:26 +08:00
|
|
|
// Same as the standard node, except the high bits of the resulting integer
|
|
|
|
// are known 0.
|
|
|
|
FP_TO_FP16,
|
|
|
|
|
2014-06-18 00:53:14 +08:00
|
|
|
/// This node is for VLIW targets and it is used to represent a vector
|
|
|
|
/// that is stored in consecutive registers with the same channel.
|
|
|
|
/// For example:
|
|
|
|
/// |X |Y|Z|W|
|
|
|
|
/// T0|v.x| | | |
|
|
|
|
/// T1|v.y| | | |
|
|
|
|
/// T2|v.z| | | |
|
|
|
|
/// T3|v.w| | | |
|
|
|
|
BUILD_VERTICAL_VECTOR,
|
2014-07-21 22:01:14 +08:00
|
|
|
/// Pointer to the start of the shader's constant data.
|
|
|
|
CONST_DATA_PTR,
|
2015-05-12 22:18:14 +08:00
|
|
|
SENDMSG,
|
2017-01-05 02:06:55 +08:00
|
|
|
SENDMSGHALT,
|
2015-05-12 23:00:46 +08:00
|
|
|
INTERP_MOV,
|
|
|
|
INTERP_P1,
|
|
|
|
INTERP_P2,
|
2016-06-15 04:29:59 +08:00
|
|
|
PC_ADD_REL_OFFSET,
|
2016-07-20 00:27:56 +08:00
|
|
|
KILL,
|
2017-01-21 05:24:26 +08:00
|
|
|
DUMMY_CHAIN,
|
2013-08-15 07:24:45 +08:00
|
|
|
FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
|
2013-08-16 09:12:06 +08:00
|
|
|
STORE_MSKOR,
|
2013-08-15 07:24:45 +08:00
|
|
|
LOAD_CONSTANT,
|
2013-09-12 10:55:14 +08:00
|
|
|
TBUFFER_STORE_FORMAT,
|
AMDGPU: Implement {BUFFER,FLAT}_ATOMIC_CMPSWAP{,_X2}
Summary:
Implement BUFFER_ATOMIC_CMPSWAP{,_X2} instructions on all GCN targets, and FLAT_ATOMIC_CMPSWAP{,_X2} on CI+.
32-bit instruction variants tested manually on Kabini and Bonaire. Tests and parts of code provided by Jan Veselý.
Patch by: Vedran Miletić
Reviewers: arsenm, tstellarAMD, nhaehnle
Subscribers: jvesely, scchan, kanarayan, arsenm
Differential Revision: http://reviews.llvm.org/D17280
llvm-svn: 265170
2016-04-02 02:27:37 +08:00
|
|
|
ATOMIC_CMP_SWAP,
|
2016-04-12 22:05:04 +08:00
|
|
|
ATOMIC_INC,
|
|
|
|
ATOMIC_DEC,
|
2016-12-21 01:19:44 +08:00
|
|
|
BUFFER_LOAD,
|
|
|
|
BUFFER_LOAD_FORMAT,
|
2012-12-12 05:25:42 +08:00
|
|
|
LAST_AMDGPU_ISD_NUMBER
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
} // End namespace AMDGPUISD
|
|
|
|
|
|
|
|
} // End namespace llvm
|
|
|
|
|
2014-08-14 00:26:38 +08:00
|
|
|
#endif
|