2018-09-07 17:05:34 +08:00
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# RUN: llc -march=amdgcn -run-pass si-fix-sgpr-copies -o - %s | FileCheck -check-prefix=GCN %s
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AMDGPU: Divergence-driven selection of scalar buffer load intrinsics
Summary:
Moving SMRD to VMEM in SIFixSGPRCopies is rather bad for performance if
the load is really uniform. So select the scalar load intrinsics directly
to either VMEM or SMRD buffer loads based on divergence analysis.
If an offset happens to end up in a VGPR -- either because a floating
point calculation was involved, or due to other remaining deficiencies
in SIFixSGPRCopies -- we use v_readfirstlane.
There is some unrelated churn in tests since we now select MUBUF offsets
in a unified way with non-scalar buffer loads.
Change-Id: I170e6816323beb1348677b358c9d380865cd1a19
Reviewers: arsenm, alex-t, rampitec, tpr
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D53283
llvm-svn: 344696
2018-10-17 23:37:30 +08:00
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# GCN-LABEL: name: smrd_vgpr_offset_imm
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# GCN: V_READFIRSTLANE_B32
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# GCN: S_BUFFER_LOAD_DWORD_SGPR
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2018-09-07 17:05:34 +08:00
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---
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name: smrd_vgpr_offset_imm
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0
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%4:vgpr_32 = COPY $vgpr0
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%3:sgpr_32 = COPY $sgpr3
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%2:sgpr_32 = COPY $sgpr2
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%1:sgpr_32 = COPY $sgpr1
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%0:sgpr_32 = COPY $sgpr0
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%5:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%6:sreg_32_xm0 = S_MOV_B32 4095
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%8:vgpr_32 = COPY %6
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%7:vgpr_32 = V_ADD_I32_e32 %4, killed %8, implicit-def dead $vcc, implicit $exec
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%10:sreg_32 = COPY %7
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%9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR killed %5, killed %10, 0
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$vgpr0 = COPY %9
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SI_RETURN_TO_EPILOG $vgpr0
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...
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2018-09-13 14:34:56 +08:00
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AMDGPU: Divergence-driven selection of scalar buffer load intrinsics
Summary:
Moving SMRD to VMEM in SIFixSGPRCopies is rather bad for performance if
the load is really uniform. So select the scalar load intrinsics directly
to either VMEM or SMRD buffer loads based on divergence analysis.
If an offset happens to end up in a VGPR -- either because a floating
point calculation was involved, or due to other remaining deficiencies
in SIFixSGPRCopies -- we use v_readfirstlane.
There is some unrelated churn in tests since we now select MUBUF offsets
in a unified way with non-scalar buffer loads.
Change-Id: I170e6816323beb1348677b358c9d380865cd1a19
Reviewers: arsenm, alex-t, rampitec, tpr
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D53283
llvm-svn: 344696
2018-10-17 23:37:30 +08:00
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# GCN-LABEL: name: smrd_vgpr_offset_imm_add_u32
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# GCN: V_READFIRSTLANE_B32
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# GCN: S_BUFFER_LOAD_DWORD_SGPR
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2018-09-13 14:34:56 +08:00
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---
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name: smrd_vgpr_offset_imm_add_u32
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0
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%4:vgpr_32 = COPY $vgpr0
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%3:sgpr_32 = COPY $sgpr3
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%2:sgpr_32 = COPY $sgpr2
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%1:sgpr_32 = COPY $sgpr1
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%0:sgpr_32 = COPY $sgpr0
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%5:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%6:sreg_32_xm0 = S_MOV_B32 4095
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%8:vgpr_32 = COPY %6
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%7:vgpr_32 = V_ADD_U32_e32 %4, killed %8, implicit $exec
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%10:sreg_32 = COPY %7
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%9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR killed %5, killed %10, 0 :: (dereferenceable invariant load 4)
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$vgpr0 = COPY %9
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SI_RETURN_TO_EPILOG $vgpr0
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...
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