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llvm-project/llvm/test/CodeGen/X86/zext-inreg-0.ll

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X86: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309774
2017-08-02 08:28:10 +08:00
; RUN: llc < %s -mtriple=i686-- | FileCheck -check-prefix=X86 %s
; RUN: llc < %s -mtriple=x86_64-- | FileCheck -check-prefix=X64 %s
Rewrite X86 codegen regression test with FileCheck llvm-svn: 180776
2013-04-30 15:51:08 +08:00
; X86-NOT: and
; X64-NOT: and
; X64-NOT: movzbq
; X64-NOT: movzwq
; X64-NOT: movzlq
Reapply r54147 with a constraint to only use the 8-bit subreg form on x86-64, to avoid the problem with x86-32 having GPRs that don't have 8-bit subregs. Also, change several 16-bit instructions to use equivalent 32-bit instructions. These have a smaller encoding and avoid partial-register updates. llvm-svn: 54223
2008-07-31 02:09:17 +08:00
; These should use movzbl instead of 'and 255'.
; This related to not having a ZERO_EXTEND_REG opcode.
Re-introduce the 8-bit subreg zext-inreg patterns for x86-32, this time using MOV32to32_ and MOV16to16_. Thanks to Evan for suggesting this. llvm-svn: 54418
2008-08-07 02:27:21 +08:00
define i32 @a(i32 %d) nounwind {
%e = add i32 %d, 1
%retval = and i32 %e, 255
ret i32 %retval
}
define i32 @b(float %d) nounwind {
%tmp12 = fptoui float %d to i8
%retval = zext i8 %tmp12 to i32
ret i32 %retval
}
Reapply r54147 with a constraint to only use the 8-bit subreg form on x86-64, to avoid the problem with x86-32 having GPRs that don't have 8-bit subregs. Also, change several 16-bit instructions to use equivalent 32-bit instructions. These have a smaller encoding and avoid partial-register updates. llvm-svn: 54223
2008-07-31 02:09:17 +08:00
define i32 @c(i32 %d) nounwind {
%e = add i32 %d, 1
%retval = and i32 %e, 65535
ret i32 %retval
}
Re-introduce the 8-bit subreg zext-inreg patterns for x86-32, this time using MOV32to32_ and MOV16to16_. Thanks to Evan for suggesting this. llvm-svn: 54418
2008-08-07 02:27:21 +08:00
define i64 @d(i64 %d) nounwind {
%e = add i64 %d, 1
%retval = and i64 %e, 255
ret i64 %retval
}
Reapply r54147 with a constraint to only use the 8-bit subreg form on x86-64, to avoid the problem with x86-32 having GPRs that don't have 8-bit subregs. Also, change several 16-bit instructions to use equivalent 32-bit instructions. These have a smaller encoding and avoid partial-register updates. llvm-svn: 54223
2008-07-31 02:09:17 +08:00
define i64 @e(i64 %d) nounwind {
%e = add i64 %d, 1
%retval = and i64 %e, 65535
ret i64 %retval
}
define i64 @f(i64 %d) nounwind {
%e = add i64 %d, 1
%retval = and i64 %e, 4294967295
ret i64 %retval
}
define i32 @g(i8 %d) nounwind {
%e = add i8 %d, 1
%retval = zext i8 %e to i32
ret i32 %retval
}
define i32 @h(i16 %d) nounwind {
%e = add i16 %d, 1
%retval = zext i16 %e to i32
ret i32 %retval
}
define i64 @i(i8 %d) nounwind {
%e = add i8 %d, 1
%retval = zext i8 %e to i64
ret i64 %retval
}
define i64 @j(i16 %d) nounwind {
%e = add i16 %d, 1
%retval = zext i16 %e to i64
ret i64 %retval
}
define i64 @k(i32 %d) nounwind {
%e = add i32 %d, 1
%retval = zext i32 %e to i64
ret i64 %retval
}