2018-11-06 03:45:37 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2015-07-09 06:35:20 +08:00
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s
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[x86] Implement combineRepeatedFPDivisors
Set the transform bar at 2 divisions because the fastest current
x86 FP divider circuit is in SandyBridge / Haswell at 10 cycle
latency (best case) relative to a 5 cycle multiplier.
So that's the worst case for this transform (no latency win),
but multiplies are obviously pipelined while divisions are not,
so there's still a big throughput win which we would expect to
show up in typical FP code.
These are the sequences I'm comparing:
divss %xmm2, %xmm0
mulss %xmm1, %xmm0
divss %xmm2, %xmm0
Becomes:
movss LCPI0_0(%rip), %xmm3 ## xmm3 = mem[0],zero,zero,zero
divss %xmm2, %xmm3
mulss %xmm3, %xmm0
mulss %xmm1, %xmm0
mulss %xmm3, %xmm0
[Ignore for the moment that we don't optimize the chain of 3 multiplies
into 2 independent fmuls followed by 1 dependent fmul...this is the DAG
version of: https://llvm.org/bugs/show_bug.cgi?id=21768 ...if we fix that,
then the transform becomes even more profitable on all targets.]
Differential Revision: http://reviews.llvm.org/D8941
llvm-svn: 235012
2015-04-15 23:22:55 +08:00
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2015-10-28 04:27:25 +08:00
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; More than one 'arcp' division using a single divisor operand
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[x86] Implement combineRepeatedFPDivisors
Set the transform bar at 2 divisions because the fastest current
x86 FP divider circuit is in SandyBridge / Haswell at 10 cycle
latency (best case) relative to a 5 cycle multiplier.
So that's the worst case for this transform (no latency win),
but multiplies are obviously pipelined while divisions are not,
so there's still a big throughput win which we would expect to
show up in typical FP code.
These are the sequences I'm comparing:
divss %xmm2, %xmm0
mulss %xmm1, %xmm0
divss %xmm2, %xmm0
Becomes:
movss LCPI0_0(%rip), %xmm3 ## xmm3 = mem[0],zero,zero,zero
divss %xmm2, %xmm3
mulss %xmm3, %xmm0
mulss %xmm1, %xmm0
mulss %xmm3, %xmm0
[Ignore for the moment that we don't optimize the chain of 3 multiplies
into 2 independent fmuls followed by 1 dependent fmul...this is the DAG
version of: https://llvm.org/bugs/show_bug.cgi?id=21768 ...if we fix that,
then the transform becomes even more profitable on all targets.]
Differential Revision: http://reviews.llvm.org/D8941
llvm-svn: 235012
2015-04-15 23:22:55 +08:00
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; should be converted into a reciprocal and multiplication.
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2015-10-28 04:27:25 +08:00
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; Don't do anything for just one division.
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define float @div1_arcp(float %x, float %y, float %z) {
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[x86] Implement combineRepeatedFPDivisors
Set the transform bar at 2 divisions because the fastest current
x86 FP divider circuit is in SandyBridge / Haswell at 10 cycle
latency (best case) relative to a 5 cycle multiplier.
So that's the worst case for this transform (no latency win),
but multiplies are obviously pipelined while divisions are not,
so there's still a big throughput win which we would expect to
show up in typical FP code.
These are the sequences I'm comparing:
divss %xmm2, %xmm0
mulss %xmm1, %xmm0
divss %xmm2, %xmm0
Becomes:
movss LCPI0_0(%rip), %xmm3 ## xmm3 = mem[0],zero,zero,zero
divss %xmm2, %xmm3
mulss %xmm3, %xmm0
mulss %xmm1, %xmm0
mulss %xmm3, %xmm0
[Ignore for the moment that we don't optimize the chain of 3 multiplies
into 2 independent fmuls followed by 1 dependent fmul...this is the DAG
version of: https://llvm.org/bugs/show_bug.cgi?id=21768 ...if we fix that,
then the transform becomes even more profitable on all targets.]
Differential Revision: http://reviews.llvm.org/D8941
llvm-svn: 235012
2015-04-15 23:22:55 +08:00
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; CHECK-LABEL: div1_arcp:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0:
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[x86] Implement combineRepeatedFPDivisors
Set the transform bar at 2 divisions because the fastest current
x86 FP divider circuit is in SandyBridge / Haswell at 10 cycle
latency (best case) relative to a 5 cycle multiplier.
So that's the worst case for this transform (no latency win),
but multiplies are obviously pipelined while divisions are not,
so there's still a big throughput win which we would expect to
show up in typical FP code.
These are the sequences I'm comparing:
divss %xmm2, %xmm0
mulss %xmm1, %xmm0
divss %xmm2, %xmm0
Becomes:
movss LCPI0_0(%rip), %xmm3 ## xmm3 = mem[0],zero,zero,zero
divss %xmm2, %xmm3
mulss %xmm3, %xmm0
mulss %xmm1, %xmm0
mulss %xmm3, %xmm0
[Ignore for the moment that we don't optimize the chain of 3 multiplies
into 2 independent fmuls followed by 1 dependent fmul...this is the DAG
version of: https://llvm.org/bugs/show_bug.cgi?id=21768 ...if we fix that,
then the transform becomes even more profitable on all targets.]
Differential Revision: http://reviews.llvm.org/D8941
llvm-svn: 235012
2015-04-15 23:22:55 +08:00
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; CHECK-NEXT: divss %xmm1, %xmm0
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; CHECK-NEXT: retq
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%div1 = fdiv arcp float %x, %y
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ret float %div1
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}
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2015-10-28 04:27:25 +08:00
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; All math instructions are 'arcp', so optimize.
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define float @div2_arcp_all(float %x, float %y, float %z) {
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; CHECK-LABEL: div2_arcp_all:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0:
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[x86] Implement combineRepeatedFPDivisors
Set the transform bar at 2 divisions because the fastest current
x86 FP divider circuit is in SandyBridge / Haswell at 10 cycle
latency (best case) relative to a 5 cycle multiplier.
So that's the worst case for this transform (no latency win),
but multiplies are obviously pipelined while divisions are not,
so there's still a big throughput win which we would expect to
show up in typical FP code.
These are the sequences I'm comparing:
divss %xmm2, %xmm0
mulss %xmm1, %xmm0
divss %xmm2, %xmm0
Becomes:
movss LCPI0_0(%rip), %xmm3 ## xmm3 = mem[0],zero,zero,zero
divss %xmm2, %xmm3
mulss %xmm3, %xmm0
mulss %xmm1, %xmm0
mulss %xmm3, %xmm0
[Ignore for the moment that we don't optimize the chain of 3 multiplies
into 2 independent fmuls followed by 1 dependent fmul...this is the DAG
version of: https://llvm.org/bugs/show_bug.cgi?id=21768 ...if we fix that,
then the transform becomes even more profitable on all targets.]
Differential Revision: http://reviews.llvm.org/D8941
llvm-svn: 235012
2015-04-15 23:22:55 +08:00
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; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
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; CHECK-NEXT: divss %xmm2, %xmm3
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; CHECK-NEXT: mulss %xmm3, %xmm0
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2015-10-28 04:27:25 +08:00
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; CHECK-NEXT: mulss %xmm1, %xmm0
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2015-07-09 06:35:20 +08:00
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; CHECK-NEXT: mulss %xmm3, %xmm0
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[x86] Implement combineRepeatedFPDivisors
Set the transform bar at 2 divisions because the fastest current
x86 FP divider circuit is in SandyBridge / Haswell at 10 cycle
latency (best case) relative to a 5 cycle multiplier.
So that's the worst case for this transform (no latency win),
but multiplies are obviously pipelined while divisions are not,
so there's still a big throughput win which we would expect to
show up in typical FP code.
These are the sequences I'm comparing:
divss %xmm2, %xmm0
mulss %xmm1, %xmm0
divss %xmm2, %xmm0
Becomes:
movss LCPI0_0(%rip), %xmm3 ## xmm3 = mem[0],zero,zero,zero
divss %xmm2, %xmm3
mulss %xmm3, %xmm0
mulss %xmm1, %xmm0
mulss %xmm3, %xmm0
[Ignore for the moment that we don't optimize the chain of 3 multiplies
into 2 independent fmuls followed by 1 dependent fmul...this is the DAG
version of: https://llvm.org/bugs/show_bug.cgi?id=21768 ...if we fix that,
then the transform becomes even more profitable on all targets.]
Differential Revision: http://reviews.llvm.org/D8941
llvm-svn: 235012
2015-04-15 23:22:55 +08:00
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; CHECK-NEXT: retq
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%div1 = fdiv arcp float %x, %z
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%mul = fmul arcp float %div1, %y
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%div2 = fdiv arcp float %mul, %z
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ret float %div2
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}
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2015-10-28 04:27:25 +08:00
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; The first division is not 'arcp', so do not optimize.
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define float @div2_arcp_partial1(float %x, float %y, float %z) {
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; CHECK-LABEL: div2_arcp_partial1:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0:
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2015-10-28 04:27:25 +08:00
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; CHECK-NEXT: divss %xmm2, %xmm0
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; CHECK-NEXT: mulss %xmm1, %xmm0
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; CHECK-NEXT: divss %xmm2, %xmm0
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; CHECK-NEXT: retq
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%div1 = fdiv float %x, %z
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%mul = fmul arcp float %div1, %y
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%div2 = fdiv arcp float %mul, %z
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ret float %div2
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}
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; The second division is not 'arcp', so do not optimize.
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define float @div2_arcp_partial2(float %x, float %y, float %z) {
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; CHECK-LABEL: div2_arcp_partial2:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0:
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2015-10-28 04:27:25 +08:00
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; CHECK-NEXT: divss %xmm2, %xmm0
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; CHECK-NEXT: mulss %xmm1, %xmm0
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; CHECK-NEXT: divss %xmm2, %xmm0
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; CHECK-NEXT: retq
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%div1 = fdiv arcp float %x, %z
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%mul = fmul arcp float %div1, %y
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%div2 = fdiv float %mul, %z
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ret float %div2
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}
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; The multiply is not 'arcp', but that does not prevent optimizing the divisions.
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define float @div2_arcp_partial3(float %x, float %y, float %z) {
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; CHECK-LABEL: div2_arcp_partial3:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0:
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2015-10-28 04:27:25 +08:00
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; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
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; CHECK-NEXT: divss %xmm2, %xmm3
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; CHECK-NEXT: mulss %xmm3, %xmm0
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; CHECK-NEXT: mulss %xmm1, %xmm0
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; CHECK-NEXT: mulss %xmm3, %xmm0
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; CHECK-NEXT: retq
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%div1 = fdiv arcp float %x, %z
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%mul = fmul float %div1, %y
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%div2 = fdiv arcp float %mul, %z
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ret float %div2
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}
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2015-07-10 01:28:37 +08:00
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; If the reciprocal is already calculated, we should not
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2018-11-06 03:45:37 +08:00
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; generate an extra multiplication by 1.0.
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2015-07-10 01:28:37 +08:00
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2015-10-28 04:27:25 +08:00
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define double @div3_arcp(double %x, double %y, double %z) {
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2015-07-10 01:28:37 +08:00
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; CHECK-LABEL: div3_arcp:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0:
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2018-11-06 03:45:37 +08:00
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; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
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2015-07-10 01:28:37 +08:00
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; CHECK-NEXT: divsd %xmm1, %xmm2
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; CHECK-NEXT: mulsd %xmm2, %xmm0
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; CHECK-NEXT: addsd %xmm2, %xmm0
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; CHECK-NEXT: retq
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%div1 = fdiv fast double 1.0, %y
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%div2 = fdiv fast double %x, %y
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%ret = fadd fast double %div2, %div1
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ret double %ret
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}
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2017-12-27 19:36:18 +08:00
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define float @div_select_constant_fold(i1 zeroext %arg) {
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; CHECK-LABEL: div_select_constant_fold:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: jne .LBB6_1
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; CHECK-NEXT: # %bb.2:
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; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB6_1:
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; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: retq
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%tmp = select i1 %arg, float 5.000000e+00, float 6.000000e+00
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%B2 = fdiv float %tmp, 1.000000e+00
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ret float %B2
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}
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define float @div_select_constant_fold_zero(i1 zeroext %arg) {
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; CHECK-LABEL: div_select_constant_fold_zero:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: jne .LBB7_1
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; CHECK-NEXT: # %bb.2:
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; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: jmp .LBB7_3
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; CHECK-NEXT: .LBB7_1:
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; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: .LBB7_3:
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; CHECK-NEXT: xorps %xmm1, %xmm1
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; CHECK-NEXT: divss %xmm1, %xmm0
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; CHECK-NEXT: retq
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%tmp = select i1 %arg, float 5.000000e+00, float 6.000000e+00
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%B2 = fdiv float %tmp, 0.000000e+00
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ret float %B2
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}
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2015-10-28 04:27:25 +08:00
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define void @PR24141() {
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2015-07-29 07:28:22 +08:00
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; CHECK-LABEL: PR24141:
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2018-11-06 03:45:37 +08:00
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: # implicit-def: $xmm0
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: .LBB8_1: # %while.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: callq g
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; CHECK-NEXT: divsd %xmm1, %xmm0
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; CHECK-NEXT: jmp .LBB8_1
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2015-07-29 07:28:22 +08:00
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entry:
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br label %while.body
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while.body:
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%x.0 = phi double [ undef, %entry ], [ %div, %while.body ]
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%call = call { double, double } @g(double %x.0)
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%xv0 = extractvalue { double, double } %call, 0
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%xv1 = extractvalue { double, double } %call, 1
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2015-10-28 04:27:25 +08:00
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%div = fdiv arcp double %xv0, %xv1
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2015-07-29 07:28:22 +08:00
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br label %while.body
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}
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declare { double, double } @g(double)
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