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llvm-project/llvm/test/CodeGen/Mips/mips64extins.ll

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Replace obsolete -mattr=n64 command line option with -target-abi=n64. No functional changes. llvm-svn: 230628
2015-02-26 20:29:48 +08:00
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
define i64 @dext(i64 %i) nounwind readnone {
entry:
[mips] Make isel select the correct DEXT variant up front. Summary: Previously, it would always select DEXT and substitute any invalid matches for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works but causes problems when adding range checked immediates to IAS. Now isel selects the correct variant up front. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16810 llvm-svn: 262229
2016-02-29 23:26:54 +08:00
; CHECK-LABEL: dext:
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
%shr = lshr i64 %i, 5
%and = and i64 %shr, 1023
ret i64 %and
}
define i64 @dextm(i64 %i) nounwind readnone {
entry:
[mips] Make isel select the correct DEXT variant up front. Summary: Previously, it would always select DEXT and substitute any invalid matches for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works but causes problems when adding range checked immediates to IAS. Now isel selects the correct variant up front. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16810 llvm-svn: 262229
2016-02-29 23:26:54 +08:00
; CHECK-LABEL: dextm:
; CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
%shr = lshr i64 %i, 5
%and = and i64 %shr, 17179869183
ret i64 %and
}
define i64 @dextu(i64 %i) nounwind readnone {
entry:
[mips] Make isel select the correct DEXT variant up front. Summary: Previously, it would always select DEXT and substitute any invalid matches for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works but causes problems when adding range checked immediates to IAS. Now isel selects the correct variant up front. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16810 llvm-svn: 262229
2016-02-29 23:26:54 +08:00
; CHECK-LABEL: dextu:
; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
%shr = lshr i64 %i, 34
%and = and i64 %shr, 63
ret i64 %and
}
define i64 @dins(i64 %i, i64 %j) nounwind readnone {
entry:
[mips] Make isel select the correct DEXT variant up front. Summary: Previously, it would always select DEXT and substitute any invalid matches for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works but causes problems when adding range checked immediates to IAS. Now isel selects the correct variant up front. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16810 llvm-svn: 262229
2016-02-29 23:26:54 +08:00
; CHECK-LABEL: dins:
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
%shl2 = shl i64 %j, 8
%and = and i64 %shl2, 261888
%and3 = and i64 %i, -261889
%or = or i64 %and3, %and
ret i64 %or
}
define i64 @dinsm(i64 %i, i64 %j) nounwind readnone {
entry:
[mips] Make isel select the correct DEXT variant up front. Summary: Previously, it would always select DEXT and substitute any invalid matches for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works but causes problems when adding range checked immediates to IAS. Now isel selects the correct variant up front. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16810 llvm-svn: 262229
2016-02-29 23:26:54 +08:00
; CHECK-LABEL: dinsm:
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 10, 33
%shl4 = shl i64 %j, 10
%and = and i64 %shl4, 8796093021184
%and5 = and i64 %i, -8796093021185
%or = or i64 %and5, %and
ret i64 %or
}
define i64 @dinsu(i64 %i, i64 %j) nounwind readnone {
entry:
[mips] Make isel select the correct DEXT variant up front. Summary: Previously, it would always select DEXT and substitute any invalid matches for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works but causes problems when adding range checked immediates to IAS. Now isel selects the correct variant up front. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16810 llvm-svn: 262229
2016-02-29 23:26:54 +08:00
; CHECK-LABEL: dinsu:
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13
%shl4 = shl i64 %j, 40
%and = and i64 %shl4, 9006099743113216
%and5 = and i64 %i, -9006099743113217
%or = or i64 %and5, %and
ret i64 %or
}