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llvm-project/clang/test/CodeGen/function-target-features.c

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Reapply r232888 after applying a fix for -msse4 code generation. As a note, any target that uses fake target features via command line options will have similar problems. llvm-svn: 233227
2015-03-26 07:14:47 +08:00
// This test verifies that we produce target-cpu and target-features attributes
// on functions when they're different from the standard cpu and have written
// features.
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-feature +avx | FileCheck %s -check-prefix=AVX-FEATURE
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-feature +avx | FileCheck %s -check-prefix=AVX-NO-CPU
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-feature +avx512f -target-feature +avx512er | FileCheck %s -check-prefix=TWO-AVX
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-cpu corei7 | FileCheck %s -check-prefix=CORE-CPU
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-cpu corei7 -target-feature +avx | FileCheck %s -check-prefix=CORE-CPU-AND-FEATURES
Always add the target-cpu and target-features sets if they're non-null. This makes sure that the front end is specific about what they're expecting the backend to produce. Update a FIXME with the idea that the target-features could be more precise using backend knowledge. llvm-svn: 235936
2015-04-28 07:11:34 +08:00
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-cpu x86-64 | FileCheck %s -check-prefix=X86-64-CPU
Reapply r232888 after applying a fix for -msse4 code generation. As a note, any target that uses fake target features via command line options will have similar problems. llvm-svn: 233227
2015-03-26 07:14:47 +08:00
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-cpu corei7-avx -target-feature -avx | FileCheck %s -check-prefix=AVX-MINUS-FEATURE
[Sparc] Add software float option -msoft-float Summary: Following patch D19265 which enable software floating point support in the Sparc backend, this patch enables the option to be enabled in the front-end using the -msoft-float option. The user should ensure a library (such as the builtins from Compiler-RT) that includes the software floating point routines is provided. Reviewers: jyknight, lero_chris Subscribers: jyknight, cfe-commits Differential Revision: http://reviews.llvm.org/D20419 llvm-svn: 270538
2016-05-24 16:30:08 +08:00
// RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm -o - %s -target-feature +soft-float | FileCheck %s -check-prefix=SOFT-FLOAT
Propagate a terrible hack to the sparc target feature handling code by erasing the soft-float target feature if the rest of the front end added it because of defaults or the soft float option. Add some testing for some of the targets that implement this hack. llvm-svn: 236179
2015-04-30 07:32:17 +08:00
// RUN: %clang_cc1 -triple arm-unknown-unknown -emit-llvm -o - %s -target-feature +soft-float | FileCheck %s -check-prefix=SOFT-FLOAT
// RUN: %clang_cc1 -triple mips-unknown-unknown -emit-llvm -o - %s -target-feature +soft-float | FileCheck %s -check-prefix=SOFT-FLOAT
Reapply r232888 after applying a fix for -msse4 code generation. As a note, any target that uses fake target features via command line options will have similar problems. llvm-svn: 233227
2015-03-26 07:14:47 +08:00
void foo() {}
Always add the target-cpu and target-features sets if they're non-null. This makes sure that the front end is specific about what they're expecting the backend to produce. Update a FIXME with the idea that the target-features could be more precise using backend knowledge. llvm-svn: 235936
2015-04-28 07:11:34 +08:00
// AVX-FEATURE: "target-features"{{.*}}+avx
Reapply r232888 after applying a fix for -msse4 code generation. As a note, any target that uses fake target features via command line options will have similar problems. llvm-svn: 233227
2015-03-26 07:14:47 +08:00
// AVX-NO-CPU-NOT: target-cpu
Use a stable sort to guarantee target feature ordering in the IR in order to make testing somewhat more feasible. Has the advantage of making it easier to find target features as well. llvm-svn: 241134
2015-07-01 09:07:12 +08:00
// TWO-AVX: "target-features"={{.*}}+avx512er{{.*}}+avx512f
Reapply r232888 after applying a fix for -msse4 code generation. As a note, any target that uses fake target features via command line options will have similar problems. llvm-svn: 233227
2015-03-26 07:14:47 +08:00
// CORE-CPU: "target-cpu"="corei7"
Always add the target-cpu and target-features sets if they're non-null. This makes sure that the front end is specific about what they're expecting the backend to produce. Update a FIXME with the idea that the target-features could be more precise using backend knowledge. llvm-svn: 235936
2015-04-28 07:11:34 +08:00
// CORE-CPU-AND-FEATURES: "target-cpu"="corei7" "target-features"={{.*}}+avx
// X86-64-CPU: "target-cpu"="x86-64"
// AVX-MINUS-FEATURE: "target-features"={{.*}}-avx
Remove the code that pulled soft float attributes out of the feature strings and remove the setting of TargetOptions::UseSoftFloat to match the code change in llvm r237079. llvm-svn: 237080
2015-05-12 09:26:21 +08:00
// SOFT-FLOAT: "target-features"={{.*}}+soft-float
// NO-SOFT-FLOAT-NOT: "target-features"={{.*}}+soft-float