llvm-project/polly/docs/experiments/matmul/main___%for.cond1.preheader...

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{
"arrays" : [
{
"name" : "MemRef_C",
"sizes" : [ "1536" ],
"type" : "float"
},
{
"name" : "MemRef_A",
"sizes" : [ "1536" ],
"type" : "float"
},
{
"name" : "MemRef_B",
"sizes" : [ "1536" ],
"type" : "float"
}
],
"context" : "{ : }",
"name" : "%for.cond1.preheader---%for.end30",
"statements" : [
{
"accesses" : [
{
"kind" : "write",
"relation" : "{ Stmt_for_body3[i0, i1] -> MemRef_C[i0, i1] }"
}
],
"domain" : "{ Stmt_for_body3[i0, i1] : 0 <= i0 <= 1535 and 0 <= i1 <= 1535 }",
"name" : "Stmt_for_body3",
"schedule" : "{ Stmt_for_body3[i0, i1] -> [0, i0, i1, 0, 0, 0, 0 ] }"
},
{
"accesses" : [
{
"kind" : "read",
"relation" : "{ Stmt_for_body8[i0, i1, i2] -> MemRef_C[i0, i1] }"
},
{
"kind" : "read",
"relation" : "{ Stmt_for_body8[i0, i1, i2] -> MemRef_A[i0, i2] }"
},
{
"kind" : "read",
"relation" : "{ Stmt_for_body8[i0, i1, i2] -> MemRef_B[i2, i1] }"
},
{
"kind" : "write",
"relation" : "{ Stmt_for_body8[i0, i1, i2] -> MemRef_C[i0, i1] }"
}
],
"domain" : "{ Stmt_for_body8[i0, i1, i2] : 0 <= i0 <= 1535 and 0 <= i1 <= 1535 and 0 <= i2 <= 1535 }",
"name" : "Stmt_for_body8",
"schedule" : "{ Stmt_for_body8[i0, i1, i2] -> [1, o0, o1, o2, i0, i2, i1]: o0 <= i0 < o0 + 64 and o1 <= i1 < o1 + 64 and o2 <= i2 < o2 + 64 and o0 % 64 = 0 and o1 % 64 = 0 and o2 % 64 = 0 }"
}
]
}