2014-05-24 20:50:23 +08:00
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//===-- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer --------------===//
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2014-03-29 18:18:08 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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2014-05-24 20:50:23 +08:00
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// of machine-dependent LLVM code to the AArch64 assembly language.
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2014-03-29 18:18:08 +08:00
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//
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//===----------------------------------------------------------------------===//
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Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot handle yet.
As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the GNU linkers
ld.bfd and ld.gold currently only support a subset of the whole range of AArch64
ELF TLS relocations. Furthermore, they assume that some of the code sequences to
access thread-local variables are produced in a very specific sequence.
When the sequence is not as the linker expects, it can silently mis-relaxe/mis-optimize
the instructions.
Even if that wouldn't be the case, it's good to produce the exact sequence,
as that ensures that linkers can perform optimizing relaxations.
This patch:
* implements support for 16MiB TLS area size instead of 4GiB TLS area size. Ideally clang
would grow an -mtls-size option to allow support for both, but that's not part of this patch.
* by default doesn't produce local dynamic access patterns, as even modern ld.bfd and ld.gold
linkers do not support the associated relocations. An option (-aarch64-elf-ldtls-generation)
is added to enable generation of local dynamic code sequence, but is off by default.
* makes sure that the exact expected code sequence for local dynamic and general dynamic
accesses is produced, by making use of a new pseudo instruction. The patch also removes
two (AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing AArch64-specific pseudo
SDNode instructions that are superseded by the new one (TLSDESC_CALLSEQ).
llvm-svn: 231227
2015-03-04 17:12:08 +08:00
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#include "MCTargetDesc/AArch64AddressingModes.h"
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2014-05-24 20:50:23 +08:00
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#include "AArch64.h"
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#include "AArch64MCInstLower.h"
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2014-07-25 19:42:14 +08:00
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#include "AArch64MachineFunctionInfo.h"
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2014-05-24 20:50:23 +08:00
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#include "AArch64RegisterInfo.h"
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#include "AArch64Subtarget.h"
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#include "InstPrinter/AArch64InstPrinter.h"
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2015-03-24 03:32:43 +08:00
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#include "MCTargetDesc/AArch64MCExpr.h"
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2014-03-29 18:18:08 +08:00
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineInstr.h"
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2014-04-16 19:52:55 +08:00
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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2014-07-25 19:42:14 +08:00
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#include "llvm/CodeGen/StackMaps.h"
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2014-04-16 19:52:55 +08:00
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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2014-03-29 18:18:08 +08:00
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DebugInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCLinkerOptimizationHint.h"
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#include "llvm/MC/MCStreamer.h"
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2015-03-06 04:04:21 +08:00
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#include "llvm/MC/MCSymbol.h"
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2016-11-17 13:15:37 +08:00
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#include "llvm/MC/MCSymbolELF.h"
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#include "llvm/MC/MCSectionELF.h"
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2016-11-23 10:07:04 +08:00
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#include "llvm/MC/MCSectionMachO.h"
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2014-03-29 18:18:08 +08:00
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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2015-03-24 03:32:43 +08:00
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#include "llvm/Support/raw_ostream.h"
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2014-03-29 18:18:08 +08:00
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using namespace llvm;
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2014-04-22 10:41:26 +08:00
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#define DEBUG_TYPE "asm-printer"
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2014-03-29 18:18:08 +08:00
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namespace {
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2014-05-24 20:50:23 +08:00
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class AArch64AsmPrinter : public AsmPrinter {
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AArch64MCInstLower MCInstLowering;
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2014-03-29 18:18:08 +08:00
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StackMaps SM;
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2016-07-07 05:39:33 +08:00
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const AArch64Subtarget *STI;
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2014-03-29 18:18:08 +08:00
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public:
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2015-01-19 04:29:04 +08:00
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AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
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2015-02-03 14:40:19 +08:00
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: AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
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2015-03-18 04:07:06 +08:00
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SM(*this), AArch64FI(nullptr) {}
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2014-03-29 18:18:08 +08:00
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2016-10-01 10:56:57 +08:00
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StringRef getPassName() const override { return "AArch64 Assembly Printer"; }
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2014-03-29 18:18:08 +08:00
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/// \brief Wrapper for MCInstLowering.lowerOperand() for the
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/// tblgen'erated pseudo lowering.
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bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
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return MCInstLowering.lowerOperand(MO, MCOp);
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}
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void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
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const MachineInstr &MI);
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void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
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const MachineInstr &MI);
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2016-11-17 13:15:37 +08:00
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void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI);
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void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI);
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void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI);
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void EmitSled(const MachineInstr &MI, SledKind Kind);
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2014-03-29 18:18:08 +08:00
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/// \brief tblgen'erated driver function for lowering simple MI->MC
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/// pseudo instructions.
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bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
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const MachineInstr *MI);
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2014-04-29 15:58:25 +08:00
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void EmitInstruction(const MachineInstr *MI) override;
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2014-03-29 18:18:08 +08:00
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2014-04-29 15:58:25 +08:00
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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2014-03-29 18:18:08 +08:00
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AsmPrinter::getAnalysisUsage(AU);
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AU.setPreservesAll();
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}
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2014-04-29 15:58:25 +08:00
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bool runOnMachineFunction(MachineFunction &F) override {
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2014-05-24 20:50:23 +08:00
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AArch64FI = F.getInfo<AArch64FunctionInfo>();
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2016-07-07 05:39:33 +08:00
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STI = static_cast<const AArch64Subtarget*>(&F.getSubtarget());
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2016-11-17 13:15:37 +08:00
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bool Result = AsmPrinter::runOnMachineFunction(F);
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2017-01-03 12:30:21 +08:00
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emitXRayTable();
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2016-11-17 13:15:37 +08:00
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return Result;
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2014-03-29 18:18:08 +08:00
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}
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private:
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void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
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bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
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bool printAsmRegInClass(const MachineOperand &MO,
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const TargetRegisterClass *RC, bool isVector,
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raw_ostream &O);
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant, const char *ExtraCode,
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2014-04-29 15:58:25 +08:00
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raw_ostream &O) override;
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2014-03-29 18:18:08 +08:00
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant, const char *ExtraCode,
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2014-04-29 15:58:25 +08:00
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raw_ostream &O) override;
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2014-03-29 18:18:08 +08:00
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void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
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2014-04-29 15:58:25 +08:00
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void EmitFunctionBodyEnd() override;
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2014-03-29 18:18:08 +08:00
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2014-04-29 15:58:25 +08:00
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MCSymbol *GetCPISymbol(unsigned CPID) const override;
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void EmitEndOfAsmFile(Module &M) override;
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2014-05-24 20:50:23 +08:00
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AArch64FunctionInfo *AArch64FI;
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2014-03-29 18:18:08 +08:00
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2014-05-24 20:50:23 +08:00
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/// \brief Emit the LOHs contained in AArch64FI.
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2014-03-29 18:18:08 +08:00
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void EmitLOHs();
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2016-07-07 05:39:33 +08:00
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/// Emit instruction to set float register to zero.
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void EmitFMov0(const MachineInstr &MI);
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2014-03-29 18:18:08 +08:00
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typedef std::map<const MachineInstr *, MCSymbol *> MInstToMCSymbol;
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MInstToMCSymbol LOHInstToLabel;
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};
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} // end of anonymous namespace
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//===----------------------------------------------------------------------===//
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2016-11-17 13:15:37 +08:00
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void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
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{
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EmitSled(MI, SledKind::FUNCTION_ENTER);
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}
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void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
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{
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EmitSled(MI, SledKind::FUNCTION_EXIT);
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}
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void AArch64AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
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{
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EmitSled(MI, SledKind::TAIL_CALL);
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}
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void AArch64AsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
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{
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static const int8_t NoopsInSledCount = 7;
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// We want to emit the following pattern:
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//
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// .Lxray_sled_N:
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// ALIGN
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// B #32
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// ; 7 NOP instructions (28 bytes)
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// .tmpN
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//
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// We need the 28 bytes (7 instructions) because at runtime, we'd be patching
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// over the full 32 bytes (8 instructions) with the following pattern:
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//
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// STP X0, X30, [SP, #-16]! ; push X0 and the link register to the stack
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// LDR W0, #12 ; W0 := function ID
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// LDR X16,#12 ; X16 := addr of __xray_FunctionEntry or __xray_FunctionExit
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// BLR X16 ; call the tracing trampoline
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// ;DATA: 32 bits of function ID
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// ;DATA: lower 32 bits of the address of the trampoline
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// ;DATA: higher 32 bits of the address of the trampoline
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// LDP X0, X30, [SP], #16 ; pop X0 and the link register from the stack
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//
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OutStreamer->EmitCodeAlignment(4);
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auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
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OutStreamer->EmitLabel(CurSled);
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auto Target = OutContext.createTempSymbol();
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// Emit "B #32" instruction, which jumps over the next 28 bytes.
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2016-11-21 11:01:43 +08:00
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// The operand has to be the number of 4-byte instructions to jump over,
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// including the current instruction.
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EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8));
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2016-11-17 13:15:37 +08:00
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for (int8_t I = 0; I < NoopsInSledCount; I++)
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EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
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OutStreamer->EmitLabel(Target);
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recordSled(CurSled, MI, Kind);
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}
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2014-05-24 20:50:23 +08:00
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void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
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2015-06-16 23:44:21 +08:00
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const Triple &TT = TM.getTargetTriple();
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2015-02-03 14:40:19 +08:00
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if (TT.isOSBinFormatMachO()) {
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2014-04-18 22:54:41 +08:00
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// Funny Darwin hack: This flag tells the linker that no global symbols
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// contain code that falls through to other global symbols (e.g. the obvious
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// implementation of multiple entry points). If this doesn't occur, the
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// linker can safely perform dead code stripping. Since LLVM never
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// generates code that does this, it is always safe to set.
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2015-04-25 03:11:51 +08:00
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OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
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2014-04-18 22:54:41 +08:00
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SM.serializeToStackMapSection();
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}
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2014-03-29 18:18:08 +08:00
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}
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2014-05-24 20:50:23 +08:00
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void AArch64AsmPrinter::EmitLOHs() {
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2014-03-29 18:18:08 +08:00
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SmallVector<MCSymbol *, 3> MCArgs;
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2014-05-24 20:50:23 +08:00
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for (const auto &D : AArch64FI->getLOHContainer()) {
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2014-03-30 03:21:20 +08:00
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for (const MachineInstr *MI : D.getArgs()) {
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MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI);
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2014-03-29 18:18:08 +08:00
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assert(LabelIt != LOHInstToLabel.end() &&
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"Label hasn't been inserted for LOH related instruction");
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MCArgs.push_back(LabelIt->second);
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}
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2015-04-25 03:11:51 +08:00
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OutStreamer->EmitLOHDirective(D.getKind(), MCArgs);
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2014-03-29 18:18:08 +08:00
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MCArgs.clear();
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}
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}
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2014-05-24 20:50:23 +08:00
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void AArch64AsmPrinter::EmitFunctionBodyEnd() {
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if (!AArch64FI->getLOHRelated().empty())
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2014-03-29 18:18:08 +08:00
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EmitLOHs();
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}
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/// GetCPISymbol - Return the symbol for the specified constant pool entry.
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2014-05-24 20:50:23 +08:00
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MCSymbol *AArch64AsmPrinter::GetCPISymbol(unsigned CPID) const {
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2014-03-29 18:18:08 +08:00
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// Darwin uses a linker-private symbol name for constant-pools (to
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// avoid addends on the relocation?), ELF has no such concept and
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// uses a normal private symbol.
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2016-10-01 13:57:55 +08:00
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if (!getDataLayout().getLinkerPrivateGlobalPrefix().empty())
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2015-05-19 02:43:14 +08:00
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return OutContext.getOrCreateSymbol(
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2014-03-29 18:18:08 +08:00
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Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
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Twine(getFunctionNumber()) + "_" + Twine(CPID));
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2015-05-19 02:43:14 +08:00
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return OutContext.getOrCreateSymbol(
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2014-03-29 18:18:08 +08:00
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Twine(getDataLayout().getPrivateGlobalPrefix()) + "CPI" +
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Twine(getFunctionNumber()) + "_" + Twine(CPID));
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}
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2014-05-24 20:50:23 +08:00
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void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
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raw_ostream &O) {
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2014-03-29 18:18:08 +08:00
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const MachineOperand &MO = MI->getOperand(OpNum);
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switch (MO.getType()) {
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default:
|
2014-06-18 13:05:13 +08:00
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llvm_unreachable("<unknown operand type>");
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2014-03-29 18:18:08 +08:00
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case MachineOperand::MO_Register: {
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unsigned Reg = MO.getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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assert(!MO.getSubReg() && "Subregs should be eliminated!");
|
2014-05-24 20:50:23 +08:00
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O << AArch64InstPrinter::getRegisterName(Reg);
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2014-03-29 18:18:08 +08:00
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break;
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}
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case MachineOperand::MO_Immediate: {
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int64_t Imm = MO.getImm();
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O << '#' << Imm;
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break;
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}
|
2015-03-06 04:04:21 +08:00
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case MachineOperand::MO_GlobalAddress: {
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const GlobalValue *GV = MO.getGlobal();
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MCSymbol *Sym = getSymbol(GV);
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// FIXME: Can we get anything other than a plain symbol here?
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assert(!MO.getTargetFlags() && "Unknown operand target flag!");
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|
2015-06-09 08:31:39 +08:00
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Sym->print(O, MAI);
|
2015-03-06 04:04:21 +08:00
|
|
|
printOffset(MO.getOffset(), O);
|
|
|
|
break;
|
|
|
|
}
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
|
|
|
|
raw_ostream &O) {
|
2014-03-29 18:18:08 +08:00
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
switch (Mode) {
|
|
|
|
default:
|
|
|
|
return true; // Unknown mode.
|
|
|
|
case 'w':
|
|
|
|
Reg = getWRegFromXReg(Reg);
|
|
|
|
break;
|
|
|
|
case 'x':
|
|
|
|
Reg = getXRegFromWReg(Reg);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
O << AArch64InstPrinter::getRegisterName(Reg);
|
2014-03-29 18:18:08 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Prints the register in MO using class RC using the offset in the
|
|
|
|
// new register class. This should not be used for cross class
|
|
|
|
// printing.
|
2014-05-24 20:50:23 +08:00
|
|
|
bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
bool isVector, raw_ostream &O) {
|
2014-03-29 18:18:08 +08:00
|
|
|
assert(MO.isReg() && "Should only get here with a register!");
|
2016-07-07 05:39:33 +08:00
|
|
|
const TargetRegisterInfo *RI = STI->getRegisterInfo();
|
2014-03-29 18:18:08 +08:00
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
|
|
|
|
assert(RI->regsOverlap(RegToPrint, Reg));
|
2014-05-24 20:50:23 +08:00
|
|
|
O << AArch64InstPrinter::getRegisterName(
|
|
|
|
RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName);
|
2014-03-29 18:18:08 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
|
|
|
|
unsigned AsmVariant,
|
|
|
|
const char *ExtraCode, raw_ostream &O) {
|
2014-03-29 18:18:08 +08:00
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
2014-05-27 15:37:21 +08:00
|
|
|
|
|
|
|
// First try the generic code, which knows about modifiers like 'c' and 'n'.
|
|
|
|
if (!AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O))
|
|
|
|
return false;
|
|
|
|
|
2014-03-29 18:18:08 +08:00
|
|
|
// Does this asm operand have a single letter operand modifier?
|
|
|
|
if (ExtraCode && ExtraCode[0]) {
|
|
|
|
if (ExtraCode[1] != 0)
|
|
|
|
return true; // Unknown modifier.
|
|
|
|
|
|
|
|
switch (ExtraCode[0]) {
|
|
|
|
default:
|
|
|
|
return true; // Unknown modifier.
|
|
|
|
case 'w': // Print W register
|
|
|
|
case 'x': // Print X register
|
|
|
|
if (MO.isReg())
|
|
|
|
return printAsmMRegister(MO, ExtraCode[0], O);
|
|
|
|
if (MO.isImm() && MO.getImm() == 0) {
|
2014-05-24 20:50:23 +08:00
|
|
|
unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
|
|
|
|
O << AArch64InstPrinter::getRegisterName(Reg);
|
2014-03-29 18:18:08 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
printOperand(MI, OpNum, O);
|
|
|
|
return false;
|
|
|
|
case 'b': // Print B register.
|
|
|
|
case 'h': // Print H register.
|
|
|
|
case 's': // Print S register.
|
|
|
|
case 'd': // Print D register.
|
|
|
|
case 'q': // Print Q register.
|
|
|
|
if (MO.isReg()) {
|
|
|
|
const TargetRegisterClass *RC;
|
|
|
|
switch (ExtraCode[0]) {
|
|
|
|
case 'b':
|
2014-05-24 20:50:23 +08:00
|
|
|
RC = &AArch64::FPR8RegClass;
|
2014-03-29 18:18:08 +08:00
|
|
|
break;
|
|
|
|
case 'h':
|
2014-05-24 20:50:23 +08:00
|
|
|
RC = &AArch64::FPR16RegClass;
|
2014-03-29 18:18:08 +08:00
|
|
|
break;
|
|
|
|
case 's':
|
2014-05-24 20:50:23 +08:00
|
|
|
RC = &AArch64::FPR32RegClass;
|
2014-03-29 18:18:08 +08:00
|
|
|
break;
|
|
|
|
case 'd':
|
2014-05-24 20:50:23 +08:00
|
|
|
RC = &AArch64::FPR64RegClass;
|
2014-03-29 18:18:08 +08:00
|
|
|
break;
|
|
|
|
case 'q':
|
2014-05-24 20:50:23 +08:00
|
|
|
RC = &AArch64::FPR128RegClass;
|
2014-03-29 18:18:08 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return printAsmRegInClass(MO, RC, false /* vector */, O);
|
|
|
|
}
|
|
|
|
printOperand(MI, OpNum, O);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// According to ARM, we should emit x and v registers unless we have a
|
|
|
|
// modifier.
|
|
|
|
if (MO.isReg()) {
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
|
|
|
|
// If this is a w or x register, print an x register.
|
2014-05-24 20:50:23 +08:00
|
|
|
if (AArch64::GPR32allRegClass.contains(Reg) ||
|
|
|
|
AArch64::GPR64allRegClass.contains(Reg))
|
2014-03-29 18:18:08 +08:00
|
|
|
return printAsmMRegister(MO, 'x', O);
|
|
|
|
|
|
|
|
// If this is a b, h, s, d, or q register, print it as a v register.
|
2014-05-24 20:50:23 +08:00
|
|
|
return printAsmRegInClass(MO, &AArch64::FPR128RegClass, true /* vector */,
|
|
|
|
O);
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
printOperand(MI, OpNum, O);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
|
|
|
unsigned OpNum,
|
|
|
|
unsigned AsmVariant,
|
|
|
|
const char *ExtraCode,
|
|
|
|
raw_ostream &O) {
|
2014-03-29 18:18:08 +08:00
|
|
|
if (ExtraCode && ExtraCode[0])
|
|
|
|
return true; // Unknown modifier.
|
|
|
|
|
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
|
|
|
assert(MO.isReg() && "unexpected inline asm memory operand");
|
2014-05-24 20:50:23 +08:00
|
|
|
O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]";
|
2014-03-29 18:18:08 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
|
|
|
|
raw_ostream &OS) {
|
2014-03-29 18:18:08 +08:00
|
|
|
unsigned NOps = MI->getNumOperands();
|
|
|
|
assert(NOps == 4);
|
|
|
|
OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
|
|
|
|
// cast away const; DIetc do not take const operands for some reason.
|
2015-04-30 00:38:44 +08:00
|
|
|
OS << cast<DILocalVariable>(MI->getOperand(NOps - 2).getMetadata())
|
2015-04-14 10:22:36 +08:00
|
|
|
->getName();
|
2014-03-29 18:18:08 +08:00
|
|
|
OS << " <- ";
|
|
|
|
// Frame address. Currently handles register +- offset only.
|
|
|
|
assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
|
|
|
|
OS << '[';
|
|
|
|
printOperand(MI, 0, OS);
|
|
|
|
OS << '+';
|
|
|
|
printOperand(MI, 1, OS);
|
|
|
|
OS << ']';
|
|
|
|
OS << "+";
|
|
|
|
printOperand(MI, NOps - 2, OS);
|
|
|
|
}
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
|
|
|
|
const MachineInstr &MI) {
|
2016-08-31 20:43:49 +08:00
|
|
|
unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes();
|
2014-03-29 18:18:08 +08:00
|
|
|
|
|
|
|
SM.recordStackMap(MI);
|
|
|
|
assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
|
2014-12-03 05:36:24 +08:00
|
|
|
|
|
|
|
// Scan ahead to trim the shadow.
|
|
|
|
const MachineBasicBlock &MBB = *MI.getParent();
|
|
|
|
MachineBasicBlock::const_iterator MII(MI);
|
|
|
|
++MII;
|
|
|
|
while (NumNOPBytes > 0) {
|
|
|
|
if (MII == MBB.end() || MII->isCall() ||
|
|
|
|
MII->getOpcode() == AArch64::DBG_VALUE ||
|
|
|
|
MII->getOpcode() == TargetOpcode::PATCHPOINT ||
|
|
|
|
MII->getOpcode() == TargetOpcode::STACKMAP)
|
|
|
|
break;
|
|
|
|
++MII;
|
|
|
|
NumNOPBytes -= 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Emit nops.
|
2014-03-29 18:18:08 +08:00
|
|
|
for (unsigned i = 0; i < NumNOPBytes; i += 4)
|
2014-05-24 20:50:23 +08:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Lower a patchpoint of the form:
|
|
|
|
// [<def>], <id>, <numBytes>, <target>, <numArgs>
|
2014-05-24 20:50:23 +08:00
|
|
|
void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
|
|
|
|
const MachineInstr &MI) {
|
2014-03-29 18:18:08 +08:00
|
|
|
SM.recordPatchPoint(MI);
|
|
|
|
|
|
|
|
PatchPointOpers Opers(&MI);
|
|
|
|
|
2016-08-24 07:33:29 +08:00
|
|
|
int64_t CallTarget = Opers.getCallTarget().getImm();
|
2014-03-29 18:18:08 +08:00
|
|
|
unsigned EncodedBytes = 0;
|
|
|
|
if (CallTarget) {
|
|
|
|
assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget &&
|
|
|
|
"High 16 bits of call target should be zero.");
|
|
|
|
unsigned ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
|
|
|
|
EncodedBytes = 16;
|
|
|
|
// Materialize the jump address:
|
2016-06-16 04:33:36 +08:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZXi)
|
2014-03-29 18:18:08 +08:00
|
|
|
.addReg(ScratchReg)
|
|
|
|
.addImm((CallTarget >> 32) & 0xFFFF)
|
|
|
|
.addImm(32));
|
2016-06-16 04:33:36 +08:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
|
2014-03-29 18:18:08 +08:00
|
|
|
.addReg(ScratchReg)
|
|
|
|
.addReg(ScratchReg)
|
|
|
|
.addImm((CallTarget >> 16) & 0xFFFF)
|
|
|
|
.addImm(16));
|
2016-06-16 04:33:36 +08:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
|
2014-03-29 18:18:08 +08:00
|
|
|
.addReg(ScratchReg)
|
|
|
|
.addReg(ScratchReg)
|
|
|
|
.addImm(CallTarget & 0xFFFF)
|
|
|
|
.addImm(0));
|
2014-05-24 20:50:23 +08:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
// Emit padding.
|
2016-08-24 07:33:29 +08:00
|
|
|
unsigned NumBytes = Opers.getNumPatchBytes();
|
2014-03-29 18:18:08 +08:00
|
|
|
assert(NumBytes >= EncodedBytes &&
|
|
|
|
"Patchpoint can't request size less than the length of a call.");
|
|
|
|
assert((NumBytes - EncodedBytes) % 4 == 0 &&
|
|
|
|
"Invalid number of NOP bytes requested!");
|
|
|
|
for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
|
2014-05-24 20:50:23 +08:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
|
2016-07-07 05:39:33 +08:00
|
|
|
void AArch64AsmPrinter::EmitFMov0(const MachineInstr &MI) {
|
|
|
|
unsigned DestReg = MI.getOperand(0).getReg();
|
|
|
|
if (STI->hasZeroCycleZeroing()) {
|
|
|
|
// Convert S/D register to corresponding Q register
|
|
|
|
if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31) {
|
|
|
|
DestReg = AArch64::Q0 + (DestReg - AArch64::S0);
|
|
|
|
} else {
|
|
|
|
assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31);
|
|
|
|
DestReg = AArch64::Q0 + (DestReg - AArch64::D0);
|
|
|
|
}
|
|
|
|
MCInst MOVI;
|
|
|
|
MOVI.setOpcode(AArch64::MOVIv2d_ns);
|
|
|
|
MOVI.addOperand(MCOperand::createReg(DestReg));
|
|
|
|
MOVI.addOperand(MCOperand::createImm(0));
|
|
|
|
EmitToStreamer(*OutStreamer, MOVI);
|
|
|
|
} else {
|
|
|
|
MCInst FMov;
|
|
|
|
switch (MI.getOpcode()) {
|
|
|
|
default: llvm_unreachable("Unexpected opcode");
|
|
|
|
case AArch64::FMOVS0:
|
|
|
|
FMov.setOpcode(AArch64::FMOVWSr);
|
|
|
|
FMov.addOperand(MCOperand::createReg(DestReg));
|
|
|
|
FMov.addOperand(MCOperand::createReg(AArch64::WZR));
|
|
|
|
break;
|
|
|
|
case AArch64::FMOVD0:
|
|
|
|
FMov.setOpcode(AArch64::FMOVXDr);
|
|
|
|
FMov.addOperand(MCOperand::createReg(DestReg));
|
|
|
|
FMov.addOperand(MCOperand::createReg(AArch64::XZR));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
EmitToStreamer(*OutStreamer, FMov);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-03-29 18:18:08 +08:00
|
|
|
// Simple pseudo-instructions have their lowering (with expansion to real
|
|
|
|
// instructions) auto-generated.
|
2014-05-24 20:50:23 +08:00
|
|
|
#include "AArch64GenMCPseudoLowering.inc"
|
2014-03-29 18:18:08 +08:00
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
2014-03-29 18:18:08 +08:00
|
|
|
// Do any auto-generated pseudo lowerings.
|
2015-04-25 03:11:51 +08:00
|
|
|
if (emitPseudoExpansionLowering(*OutStreamer, MI))
|
2014-03-29 18:18:08 +08:00
|
|
|
return;
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
if (AArch64FI->getLOHRelated().count(MI)) {
|
2014-03-29 18:18:08 +08:00
|
|
|
// Generate a label for LOH related instruction
|
2015-03-18 04:07:06 +08:00
|
|
|
MCSymbol *LOHLabel = createTempSymbol("loh");
|
2014-03-29 18:18:08 +08:00
|
|
|
// Associate the instruction with the label
|
|
|
|
LOHInstToLabel[MI] = LOHLabel;
|
2015-04-25 03:11:51 +08:00
|
|
|
OutStreamer->EmitLabel(LOHLabel);
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Do any manual lowerings.
|
|
|
|
switch (MI->getOpcode()) {
|
|
|
|
default:
|
|
|
|
break;
|
2014-05-24 20:50:23 +08:00
|
|
|
case AArch64::DBG_VALUE: {
|
2015-04-25 03:11:51 +08:00
|
|
|
if (isVerbose() && OutStreamer->hasRawTextSupport()) {
|
2014-03-29 18:18:08 +08:00
|
|
|
SmallString<128> TmpStr;
|
|
|
|
raw_svector_ostream OS(TmpStr);
|
|
|
|
PrintDebugValueComment(MI, OS);
|
2015-04-25 03:11:51 +08:00
|
|
|
OutStreamer->EmitRawText(StringRef(OS.str()));
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Tail calls use pseudo instructions so they have the proper code-gen
|
|
|
|
// attributes (isCall, isReturn, etc.). We lower them to the real
|
|
|
|
// instruction here.
|
2014-05-24 20:50:23 +08:00
|
|
|
case AArch64::TCRETURNri: {
|
2014-03-29 18:18:08 +08:00
|
|
|
MCInst TmpInst;
|
2014-05-24 20:50:23 +08:00
|
|
|
TmpInst.setOpcode(AArch64::BR);
|
2015-05-14 02:37:00 +08:00
|
|
|
TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
|
2015-04-25 03:11:51 +08:00
|
|
|
EmitToStreamer(*OutStreamer, TmpInst);
|
2014-03-29 18:18:08 +08:00
|
|
|
return;
|
|
|
|
}
|
2014-05-24 20:50:23 +08:00
|
|
|
case AArch64::TCRETURNdi: {
|
2014-03-29 18:18:08 +08:00
|
|
|
MCOperand Dest;
|
|
|
|
MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
|
|
|
|
MCInst TmpInst;
|
2014-05-24 20:50:23 +08:00
|
|
|
TmpInst.setOpcode(AArch64::B);
|
2014-03-29 18:18:08 +08:00
|
|
|
TmpInst.addOperand(Dest);
|
2015-04-25 03:11:51 +08:00
|
|
|
EmitToStreamer(*OutStreamer, TmpInst);
|
2014-03-29 18:18:08 +08:00
|
|
|
return;
|
|
|
|
}
|
Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot handle yet.
As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the GNU linkers
ld.bfd and ld.gold currently only support a subset of the whole range of AArch64
ELF TLS relocations. Furthermore, they assume that some of the code sequences to
access thread-local variables are produced in a very specific sequence.
When the sequence is not as the linker expects, it can silently mis-relaxe/mis-optimize
the instructions.
Even if that wouldn't be the case, it's good to produce the exact sequence,
as that ensures that linkers can perform optimizing relaxations.
This patch:
* implements support for 16MiB TLS area size instead of 4GiB TLS area size. Ideally clang
would grow an -mtls-size option to allow support for both, but that's not part of this patch.
* by default doesn't produce local dynamic access patterns, as even modern ld.bfd and ld.gold
linkers do not support the associated relocations. An option (-aarch64-elf-ldtls-generation)
is added to enable generation of local dynamic code sequence, but is off by default.
* makes sure that the exact expected code sequence for local dynamic and general dynamic
accesses is produced, by making use of a new pseudo instruction. The patch also removes
two (AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing AArch64-specific pseudo
SDNode instructions that are superseded by the new one (TLSDESC_CALLSEQ).
llvm-svn: 231227
2015-03-04 17:12:08 +08:00
|
|
|
case AArch64::TLSDESC_CALLSEQ: {
|
|
|
|
/// lower this to:
|
|
|
|
/// adrp x0, :tlsdesc:var
|
|
|
|
/// ldr x1, [x0, #:tlsdesc_lo12:var]
|
|
|
|
/// add x0, x0, #:tlsdesc_lo12:var
|
|
|
|
/// .tlsdesccall var
|
|
|
|
/// blr x1
|
|
|
|
/// (TPIDR_EL0 offset now in x0)
|
|
|
|
const MachineOperand &MO_Sym = MI->getOperand(0);
|
|
|
|
MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
|
|
|
|
MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
|
[AArch64] ILP32 Backend Relocation Support
Remove "_NC" suffix and semantics from TLSDESC_LD{64,32}_LO12 and
TLSDESC_ADD_LO12 relocations
Rearrange ordering in AArch64.def to follow relocation encoding
Fix name:
R_AARCH64_P32_LD64_GOT_LO12_NC => R_AARCH64_P32_LD32_GOT_LO12_NC
Add support for several "TLS", "TLSGD", and "TLSLD" relocations for
ILP32
Fix return values from isNonILP32reloc
Add implementations for
R_AARCH64_ADR_PREL_PG_HI21_NC, R_AARCH64_P32_LD32_GOT_LO12_NC,
R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC,
R_AARCH64_P32_TLSDESC_LD32_LO12, R_AARCH64_LD64_GOT_LO12_NC,
*TLSLD_LDST128_DTPREL_LO12, *TLSLD_LDST128_DTPREL_LO12_NC,
*TLSLE_LDST128_TPREL_LO12, *TLSLE_LDST128_TPREL_LO12_NC
Modify error messages to give name of equivalent relocation in the
ABI not being used, along with better checking for non-existent
requested relocations.
Added assembler support for "pg_hi21_nc"
Relocation definitions added without implementations:
R_AARCH64_P32_TLSDESC_ADR_PREL21, R_AARCH64_P32_TLSGD_ADR_PREL21,
R_AARCH64_P32_TLSGD_ADD_LO12_NC, R_AARCH64_P32_TLSLD_ADR_PREL21,
R_AARCH64_P32_TLSLD_ADR_PAGE21, R_AARCH64_P32_TLSLD_ADD_LO12_NC,
R_AARCH64_P32_TLSLD_LD_PREL19, R_AARCH64_P32_TLSDESC_LD_PREL19,
R_AARCH64_P32_TLSGD_ADR_PAGE21, R_AARCH64_P32_TLS_DTPREL,
R_AARCH64_P32_TLS_DTPMOD, R_AARCH64_P32_TLS_TPREL,
R_AARCH64_P32_TLSDESC
Fix encoding:
R_AARCH64_P32_TLSDESC_ADR_PAGE21
Reviewers: Peter Smith
Patch by: Joel Jones (jjones@cavium.com)
Differential Revision: https://reviews.llvm.org/D32072
llvm-svn: 301980
2017-05-03 06:01:48 +08:00
|
|
|
MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF);
|
Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot handle yet.
As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the GNU linkers
ld.bfd and ld.gold currently only support a subset of the whole range of AArch64
ELF TLS relocations. Furthermore, they assume that some of the code sequences to
access thread-local variables are produced in a very specific sequence.
When the sequence is not as the linker expects, it can silently mis-relaxe/mis-optimize
the instructions.
Even if that wouldn't be the case, it's good to produce the exact sequence,
as that ensures that linkers can perform optimizing relaxations.
This patch:
* implements support for 16MiB TLS area size instead of 4GiB TLS area size. Ideally clang
would grow an -mtls-size option to allow support for both, but that's not part of this patch.
* by default doesn't produce local dynamic access patterns, as even modern ld.bfd and ld.gold
linkers do not support the associated relocations. An option (-aarch64-elf-ldtls-generation)
is added to enable generation of local dynamic code sequence, but is off by default.
* makes sure that the exact expected code sequence for local dynamic and general dynamic
accesses is produced, by making use of a new pseudo instruction. The patch also removes
two (AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing AArch64-specific pseudo
SDNode instructions that are superseded by the new one (TLSDESC_CALLSEQ).
llvm-svn: 231227
2015-03-04 17:12:08 +08:00
|
|
|
MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
|
|
|
|
MCInstLowering.lowerOperand(MO_Sym, Sym);
|
|
|
|
MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
|
|
|
|
MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
|
|
|
|
|
|
|
|
MCInst Adrp;
|
|
|
|
Adrp.setOpcode(AArch64::ADRP);
|
2015-05-14 02:37:00 +08:00
|
|
|
Adrp.addOperand(MCOperand::createReg(AArch64::X0));
|
Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot handle yet.
As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the GNU linkers
ld.bfd and ld.gold currently only support a subset of the whole range of AArch64
ELF TLS relocations. Furthermore, they assume that some of the code sequences to
access thread-local variables are produced in a very specific sequence.
When the sequence is not as the linker expects, it can silently mis-relaxe/mis-optimize
the instructions.
Even if that wouldn't be the case, it's good to produce the exact sequence,
as that ensures that linkers can perform optimizing relaxations.
This patch:
* implements support for 16MiB TLS area size instead of 4GiB TLS area size. Ideally clang
would grow an -mtls-size option to allow support for both, but that's not part of this patch.
* by default doesn't produce local dynamic access patterns, as even modern ld.bfd and ld.gold
linkers do not support the associated relocations. An option (-aarch64-elf-ldtls-generation)
is added to enable generation of local dynamic code sequence, but is off by default.
* makes sure that the exact expected code sequence for local dynamic and general dynamic
accesses is produced, by making use of a new pseudo instruction. The patch also removes
two (AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing AArch64-specific pseudo
SDNode instructions that are superseded by the new one (TLSDESC_CALLSEQ).
llvm-svn: 231227
2015-03-04 17:12:08 +08:00
|
|
|
Adrp.addOperand(SymTLSDesc);
|
2015-04-25 03:11:51 +08:00
|
|
|
EmitToStreamer(*OutStreamer, Adrp);
|
Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot handle yet.
As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the GNU linkers
ld.bfd and ld.gold currently only support a subset of the whole range of AArch64
ELF TLS relocations. Furthermore, they assume that some of the code sequences to
access thread-local variables are produced in a very specific sequence.
When the sequence is not as the linker expects, it can silently mis-relaxe/mis-optimize
the instructions.
Even if that wouldn't be the case, it's good to produce the exact sequence,
as that ensures that linkers can perform optimizing relaxations.
This patch:
* implements support for 16MiB TLS area size instead of 4GiB TLS area size. Ideally clang
would grow an -mtls-size option to allow support for both, but that's not part of this patch.
* by default doesn't produce local dynamic access patterns, as even modern ld.bfd and ld.gold
linkers do not support the associated relocations. An option (-aarch64-elf-ldtls-generation)
is added to enable generation of local dynamic code sequence, but is off by default.
* makes sure that the exact expected code sequence for local dynamic and general dynamic
accesses is produced, by making use of a new pseudo instruction. The patch also removes
two (AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing AArch64-specific pseudo
SDNode instructions that are superseded by the new one (TLSDESC_CALLSEQ).
llvm-svn: 231227
2015-03-04 17:12:08 +08:00
|
|
|
|
|
|
|
MCInst Ldr;
|
|
|
|
Ldr.setOpcode(AArch64::LDRXui);
|
2015-05-14 02:37:00 +08:00
|
|
|
Ldr.addOperand(MCOperand::createReg(AArch64::X1));
|
|
|
|
Ldr.addOperand(MCOperand::createReg(AArch64::X0));
|
Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot handle yet.
As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the GNU linkers
ld.bfd and ld.gold currently only support a subset of the whole range of AArch64
ELF TLS relocations. Furthermore, they assume that some of the code sequences to
access thread-local variables are produced in a very specific sequence.
When the sequence is not as the linker expects, it can silently mis-relaxe/mis-optimize
the instructions.
Even if that wouldn't be the case, it's good to produce the exact sequence,
as that ensures that linkers can perform optimizing relaxations.
This patch:
* implements support for 16MiB TLS area size instead of 4GiB TLS area size. Ideally clang
would grow an -mtls-size option to allow support for both, but that's not part of this patch.
* by default doesn't produce local dynamic access patterns, as even modern ld.bfd and ld.gold
linkers do not support the associated relocations. An option (-aarch64-elf-ldtls-generation)
is added to enable generation of local dynamic code sequence, but is off by default.
* makes sure that the exact expected code sequence for local dynamic and general dynamic
accesses is produced, by making use of a new pseudo instruction. The patch also removes
two (AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing AArch64-specific pseudo
SDNode instructions that are superseded by the new one (TLSDESC_CALLSEQ).
llvm-svn: 231227
2015-03-04 17:12:08 +08:00
|
|
|
Ldr.addOperand(SymTLSDescLo12);
|
2015-05-14 02:37:00 +08:00
|
|
|
Ldr.addOperand(MCOperand::createImm(0));
|
2015-04-25 03:11:51 +08:00
|
|
|
EmitToStreamer(*OutStreamer, Ldr);
|
Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot handle yet.
As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the GNU linkers
ld.bfd and ld.gold currently only support a subset of the whole range of AArch64
ELF TLS relocations. Furthermore, they assume that some of the code sequences to
access thread-local variables are produced in a very specific sequence.
When the sequence is not as the linker expects, it can silently mis-relaxe/mis-optimize
the instructions.
Even if that wouldn't be the case, it's good to produce the exact sequence,
as that ensures that linkers can perform optimizing relaxations.
This patch:
* implements support for 16MiB TLS area size instead of 4GiB TLS area size. Ideally clang
would grow an -mtls-size option to allow support for both, but that's not part of this patch.
* by default doesn't produce local dynamic access patterns, as even modern ld.bfd and ld.gold
linkers do not support the associated relocations. An option (-aarch64-elf-ldtls-generation)
is added to enable generation of local dynamic code sequence, but is off by default.
* makes sure that the exact expected code sequence for local dynamic and general dynamic
accesses is produced, by making use of a new pseudo instruction. The patch also removes
two (AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing AArch64-specific pseudo
SDNode instructions that are superseded by the new one (TLSDESC_CALLSEQ).
llvm-svn: 231227
2015-03-04 17:12:08 +08:00
|
|
|
|
|
|
|
MCInst Add;
|
|
|
|
Add.setOpcode(AArch64::ADDXri);
|
2015-05-14 02:37:00 +08:00
|
|
|
Add.addOperand(MCOperand::createReg(AArch64::X0));
|
|
|
|
Add.addOperand(MCOperand::createReg(AArch64::X0));
|
Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot handle yet.
As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the GNU linkers
ld.bfd and ld.gold currently only support a subset of the whole range of AArch64
ELF TLS relocations. Furthermore, they assume that some of the code sequences to
access thread-local variables are produced in a very specific sequence.
When the sequence is not as the linker expects, it can silently mis-relaxe/mis-optimize
the instructions.
Even if that wouldn't be the case, it's good to produce the exact sequence,
as that ensures that linkers can perform optimizing relaxations.
This patch:
* implements support for 16MiB TLS area size instead of 4GiB TLS area size. Ideally clang
would grow an -mtls-size option to allow support for both, but that's not part of this patch.
* by default doesn't produce local dynamic access patterns, as even modern ld.bfd and ld.gold
linkers do not support the associated relocations. An option (-aarch64-elf-ldtls-generation)
is added to enable generation of local dynamic code sequence, but is off by default.
* makes sure that the exact expected code sequence for local dynamic and general dynamic
accesses is produced, by making use of a new pseudo instruction. The patch also removes
two (AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing AArch64-specific pseudo
SDNode instructions that are superseded by the new one (TLSDESC_CALLSEQ).
llvm-svn: 231227
2015-03-04 17:12:08 +08:00
|
|
|
Add.addOperand(SymTLSDescLo12);
|
2015-05-14 02:37:00 +08:00
|
|
|
Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
|
2015-04-25 03:11:51 +08:00
|
|
|
EmitToStreamer(*OutStreamer, Add);
|
Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot handle yet.
As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the GNU linkers
ld.bfd and ld.gold currently only support a subset of the whole range of AArch64
ELF TLS relocations. Furthermore, they assume that some of the code sequences to
access thread-local variables are produced in a very specific sequence.
When the sequence is not as the linker expects, it can silently mis-relaxe/mis-optimize
the instructions.
Even if that wouldn't be the case, it's good to produce the exact sequence,
as that ensures that linkers can perform optimizing relaxations.
This patch:
* implements support for 16MiB TLS area size instead of 4GiB TLS area size. Ideally clang
would grow an -mtls-size option to allow support for both, but that's not part of this patch.
* by default doesn't produce local dynamic access patterns, as even modern ld.bfd and ld.gold
linkers do not support the associated relocations. An option (-aarch64-elf-ldtls-generation)
is added to enable generation of local dynamic code sequence, but is off by default.
* makes sure that the exact expected code sequence for local dynamic and general dynamic
accesses is produced, by making use of a new pseudo instruction. The patch also removes
two (AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing AArch64-specific pseudo
SDNode instructions that are superseded by the new one (TLSDESC_CALLSEQ).
llvm-svn: 231227
2015-03-04 17:12:08 +08:00
|
|
|
|
|
|
|
// Emit a relocation-annotation. This expands to no code, but requests
|
2014-03-29 18:18:08 +08:00
|
|
|
// the following instruction gets an R_AARCH64_TLSDESC_CALL.
|
|
|
|
MCInst TLSDescCall;
|
2014-05-24 20:50:23 +08:00
|
|
|
TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
|
2014-03-29 18:18:08 +08:00
|
|
|
TLSDescCall.addOperand(Sym);
|
2015-04-25 03:11:51 +08:00
|
|
|
EmitToStreamer(*OutStreamer, TLSDescCall);
|
2014-03-29 18:18:08 +08:00
|
|
|
|
Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot handle yet.
As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the GNU linkers
ld.bfd and ld.gold currently only support a subset of the whole range of AArch64
ELF TLS relocations. Furthermore, they assume that some of the code sequences to
access thread-local variables are produced in a very specific sequence.
When the sequence is not as the linker expects, it can silently mis-relaxe/mis-optimize
the instructions.
Even if that wouldn't be the case, it's good to produce the exact sequence,
as that ensures that linkers can perform optimizing relaxations.
This patch:
* implements support for 16MiB TLS area size instead of 4GiB TLS area size. Ideally clang
would grow an -mtls-size option to allow support for both, but that's not part of this patch.
* by default doesn't produce local dynamic access patterns, as even modern ld.bfd and ld.gold
linkers do not support the associated relocations. An option (-aarch64-elf-ldtls-generation)
is added to enable generation of local dynamic code sequence, but is off by default.
* makes sure that the exact expected code sequence for local dynamic and general dynamic
accesses is produced, by making use of a new pseudo instruction. The patch also removes
two (AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing AArch64-specific pseudo
SDNode instructions that are superseded by the new one (TLSDESC_CALLSEQ).
llvm-svn: 231227
2015-03-04 17:12:08 +08:00
|
|
|
MCInst Blr;
|
|
|
|
Blr.setOpcode(AArch64::BLR);
|
2015-05-14 02:37:00 +08:00
|
|
|
Blr.addOperand(MCOperand::createReg(AArch64::X1));
|
2015-04-25 03:11:51 +08:00
|
|
|
EmitToStreamer(*OutStreamer, Blr);
|
2014-03-29 18:18:08 +08:00
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-07-07 05:39:33 +08:00
|
|
|
case AArch64::FMOVS0:
|
|
|
|
case AArch64::FMOVD0:
|
|
|
|
EmitFMov0(*MI);
|
|
|
|
return;
|
|
|
|
|
2014-03-29 18:18:08 +08:00
|
|
|
case TargetOpcode::STACKMAP:
|
2015-04-25 03:11:51 +08:00
|
|
|
return LowerSTACKMAP(*OutStreamer, SM, *MI);
|
2014-03-29 18:18:08 +08:00
|
|
|
|
|
|
|
case TargetOpcode::PATCHPOINT:
|
2015-04-25 03:11:51 +08:00
|
|
|
return LowerPATCHPOINT(*OutStreamer, SM, *MI);
|
2016-11-17 13:15:37 +08:00
|
|
|
|
|
|
|
case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
|
|
|
|
LowerPATCHABLE_FUNCTION_ENTER(*MI);
|
|
|
|
return;
|
|
|
|
|
|
|
|
case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
|
|
|
|
LowerPATCHABLE_FUNCTION_EXIT(*MI);
|
|
|
|
return;
|
|
|
|
|
|
|
|
case TargetOpcode::PATCHABLE_TAIL_CALL:
|
|
|
|
LowerPATCHABLE_TAIL_CALL(*MI);
|
|
|
|
return;
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Finally, do the automated lowerings for everything else.
|
|
|
|
MCInst TmpInst;
|
|
|
|
MCInstLowering.Lower(MI, TmpInst);
|
2015-04-25 03:11:51 +08:00
|
|
|
EmitToStreamer(*OutStreamer, TmpInst);
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Force static initialization.
|
2014-05-24 20:50:23 +08:00
|
|
|
extern "C" void LLVMInitializeAArch64AsmPrinter() {
|
2016-10-10 07:00:34 +08:00
|
|
|
RegisterAsmPrinter<AArch64AsmPrinter> X(getTheAArch64leTarget());
|
|
|
|
RegisterAsmPrinter<AArch64AsmPrinter> Y(getTheAArch64beTarget());
|
|
|
|
RegisterAsmPrinter<AArch64AsmPrinter> Z(getTheARM64Target());
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|