2012-02-17 09:23:50 +08:00
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//===-- MipsAsmPrinter.h - Mips LLVM Assembly Printer ----------*- C++ -*--===//
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2011-07-08 04:10:52 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Mips Assembly printer class.
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//
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//===----------------------------------------------------------------------===//
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2014-08-14 00:26:38 +08:00
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSASMPRINTER_H
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#define LLVM_LIB_TARGET_MIPS_MIPSASMPRINTER_H
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2011-07-08 04:10:52 +08:00
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2014-02-15 03:16:39 +08:00
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#include "Mips16HardFloatInfo.h"
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2012-03-28 08:22:50 +08:00
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#include "MipsMCInstLower.h"
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2012-12-04 15:12:27 +08:00
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#include "MipsMachineFunction.h"
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2011-07-08 04:10:52 +08:00
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#include "MipsSubtarget.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class MCStreamer;
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class MachineInstr;
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class MachineBasicBlock;
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2013-10-08 21:08:17 +08:00
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class MipsTargetStreamer;
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2011-07-08 04:10:52 +08:00
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class Module;
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2012-03-18 02:46:09 +08:00
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class raw_ostream;
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2011-07-08 04:10:52 +08:00
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class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter {
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2013-10-08 21:08:17 +08:00
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MipsTargetStreamer &getTargetStreamer();
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2011-11-24 06:19:28 +08:00
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2012-03-28 08:22:50 +08:00
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void EmitInstrWithMacroNoAT(const MachineInstr *MI);
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2012-09-27 09:59:07 +08:00
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private:
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// tblgen'erated function.
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bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
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const MachineInstr *MI);
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2014-07-09 18:21:59 +08:00
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// Emit PseudoReturn, PseudoReturn64, PseudoIndirectBranch,
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// and PseudoIndirectBranch64 as a JR, JR_MM, JALR, or JALR64 as appropriate
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// for the target.
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void emitPseudoIndirectBranch(MCStreamer &OutStreamer,
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const MachineInstr *MI);
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[mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6)
Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.
Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise
On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.
Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.
The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').
Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().
Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4268
llvm-svn: 212604
2014-07-09 18:16:07 +08:00
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2012-09-27 09:59:07 +08:00
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// lowerOperand - Convert a MachineOperand into the equivalent MCOperand.
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bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp);
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2013-10-28 05:57:36 +08:00
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/// MCP - Keep a pointer to constantpool entries of the current
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/// MachineFunction.
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const MachineConstantPool *MCP;
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/// InConstantPool - Maintain state when emitting a sequence of constant
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/// pool entries so we can properly mark them as data regions.
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bool InConstantPool;
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2014-02-15 03:16:39 +08:00
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std::map<const char *, const llvm::Mips16HardFloatInfo::FuncSignature *>
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StubsNeeded;
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void EmitJal(MCSymbol *Symbol);
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void EmitInstrReg(unsigned Opcode, unsigned Reg);
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void EmitInstrRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2);
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void EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2,
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unsigned Reg3);
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void EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1, unsigned Reg2,
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unsigned FPReg1, unsigned FPReg2, bool LE);
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void EmitSwapFPIntParams(Mips16HardFloatInfo::FPParamVariant, bool LE,
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bool ToFP);
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void EmitSwapFPIntRetval(Mips16HardFloatInfo::FPReturnVariant, bool LE);
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void EmitFPCallStub(const char *, const Mips16HardFloatInfo::FuncSignature *);
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2013-10-28 05:57:36 +08:00
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2014-02-28 18:00:38 +08:00
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void NaClAlignIndirectJumpTargets(MachineFunction &MF);
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2014-04-30 23:06:25 +08:00
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bool isLongBranchPseudo(int Opcode) const;
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2011-07-08 04:10:52 +08:00
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public:
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2011-11-24 06:19:28 +08:00
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const MipsSubtarget *Subtarget;
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2012-03-28 08:22:50 +08:00
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const MipsFunctionInfo *MipsFI;
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MipsMCInstLower MCInstLowering;
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2011-11-24 06:19:28 +08:00
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2014-07-18 08:08:53 +08:00
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// We initialize the subtarget here and in runOnMachineFunction
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// since there are certain target specific flags (ABI) that could
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// reside on the TargetMachine, but are on the subtarget currently
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// and we need them for the beginning of file output before we've
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// seen a single function.
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explicit MipsAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
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: AsmPrinter(TM, Streamer), MCP(nullptr), InConstantPool(false),
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Subtarget(&TM.getSubtarget<MipsSubtarget>()), MCInstLowering(*this) {}
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2011-07-08 04:10:52 +08:00
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2014-04-29 15:58:02 +08:00
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const char *getPassName() const override {
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2011-07-08 04:10:52 +08:00
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return "Mips Assembly Printer";
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}
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2014-04-29 15:58:02 +08:00
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bool runOnMachineFunction(MachineFunction &MF) override;
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2012-03-28 08:22:50 +08:00
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2014-04-29 15:58:02 +08:00
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void EmitConstantPool() override {
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2013-11-27 04:38:40 +08:00
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bool UsingConstantPools =
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(Subtarget->inMips16Mode() && Subtarget->useConstantIslands());
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2013-10-28 05:57:36 +08:00
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if (!UsingConstantPools)
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AsmPrinter::EmitConstantPool();
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// we emit constant pools customly!
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}
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2014-04-29 15:58:02 +08:00
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void EmitInstruction(const MachineInstr *MI) override;
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2014-01-27 12:33:11 +08:00
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void printSavedRegsBitmask();
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2011-07-08 04:10:52 +08:00
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void emitFrameDirective();
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const char *getCurrentABIString() const;
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2014-04-29 15:58:02 +08:00
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void EmitFunctionEntryLabel() override;
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void EmitFunctionBodyStart() override;
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void EmitFunctionBodyEnd() override;
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bool isBlockOnlyReachableByFallthrough(
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const MachineBasicBlock* MBB) const override;
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2011-07-08 04:10:52 +08:00
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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2014-04-29 15:58:02 +08:00
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raw_ostream &O) override;
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2011-07-08 04:10:52 +08:00
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant, const char *ExtraCode,
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2014-04-29 15:58:02 +08:00
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raw_ostream &O) override;
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2011-07-08 04:10:52 +08:00
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void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
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void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
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2013-11-12 18:45:18 +08:00
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void printUnsignedImm8(const MachineInstr *MI, int opNum, raw_ostream &O);
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2011-07-08 04:54:20 +08:00
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void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
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void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O);
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2011-07-08 04:10:52 +08:00
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void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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2014-04-28 12:05:08 +08:00
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const char *Modifier = nullptr);
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2014-11-20 00:44:02 +08:00
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void printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O);
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2014-04-29 15:58:02 +08:00
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void EmitStartOfAsmFile(Module &M) override;
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void EmitEndOfAsmFile(Module &M) override;
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2011-07-08 04:10:52 +08:00
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void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
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};
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}
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#endif
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