2016-11-15 14:34:33 +08:00
|
|
|
//===-- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering -----------===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
///
|
|
|
|
/// \file
|
|
|
|
/// This file implements the lowering of LLVM calls to machine code calls for
|
|
|
|
/// GlobalISel.
|
|
|
|
///
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#include "X86CallLowering.h"
|
|
|
|
#include "X86ISelLowering.h"
|
|
|
|
#include "X86InstrInfo.h"
|
2017-01-29 16:35:42 +08:00
|
|
|
#include "X86TargetMachine.h"
|
|
|
|
#include "X86CallingConv.h"
|
|
|
|
|
2016-11-15 14:34:33 +08:00
|
|
|
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
|
2017-01-29 16:35:42 +08:00
|
|
|
#include "llvm/CodeGen/MachineValueType.h"
|
|
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
|
|
#include "llvm/Target/TargetSubtargetInfo.h"
|
2016-11-15 14:34:33 +08:00
|
|
|
|
|
|
|
using namespace llvm;
|
|
|
|
|
2017-01-29 16:35:42 +08:00
|
|
|
#include "X86GenCallingConv.inc"
|
|
|
|
|
2016-11-15 14:34:33 +08:00
|
|
|
#ifndef LLVM_BUILD_GLOBAL_ISEL
|
|
|
|
#error "This shouldn't be built without GISel"
|
|
|
|
#endif
|
|
|
|
|
|
|
|
X86CallLowering::X86CallLowering(const X86TargetLowering &TLI)
|
|
|
|
: CallLowering(&TLI) {}
|
|
|
|
|
2017-02-06 16:37:41 +08:00
|
|
|
void X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
|
|
|
|
SmallVectorImpl<ArgInfo> &SplitArgs,
|
|
|
|
const DataLayout &DL,
|
|
|
|
MachineRegisterInfo &MRI,
|
|
|
|
SplitArgTy PerformArgSplit) const {
|
|
|
|
|
|
|
|
const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
|
|
|
|
LLVMContext &Context = OrigArg.Ty->getContext();
|
|
|
|
EVT VT = TLI.getValueType(DL, OrigArg.Ty);
|
|
|
|
unsigned NumParts = TLI.getNumRegisters(Context, VT);
|
|
|
|
|
|
|
|
if (NumParts == 1) {
|
|
|
|
SplitArgs.push_back(OrigArg);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
SmallVector<uint64_t, 4> BitOffsets;
|
|
|
|
SmallVector<unsigned, 8> SplitRegs;
|
|
|
|
|
|
|
|
EVT PartVT = TLI.getRegisterType(Context, VT);
|
|
|
|
Type *PartTy = PartVT.getTypeForEVT(Context);
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < NumParts; ++i) {
|
2017-03-08 03:21:23 +08:00
|
|
|
ArgInfo Info = ArgInfo{MRI.createGenericVirtualRegister(LLT{*PartTy, DL}),
|
|
|
|
PartTy, OrigArg.Flags};
|
2017-02-06 16:37:41 +08:00
|
|
|
SplitArgs.push_back(Info);
|
2017-03-07 07:50:28 +08:00
|
|
|
PerformArgSplit(Info.Reg, PartVT.getSizeInBits() * i);
|
2017-02-06 16:37:41 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
namespace {
|
|
|
|
struct FuncReturnHandler : public CallLowering::ValueHandler {
|
|
|
|
FuncReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
|
|
|
|
MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
|
|
|
|
: ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
|
|
|
|
|
|
|
|
unsigned getStackAddress(uint64_t Size, int64_t Offset,
|
|
|
|
MachinePointerInfo &MPO) override {
|
|
|
|
llvm_unreachable("Don't know how to get a stack address yet");
|
|
|
|
}
|
|
|
|
|
|
|
|
void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
|
|
|
|
CCValAssign &VA) override {
|
|
|
|
MIB.addUse(PhysReg, RegState::Implicit);
|
|
|
|
unsigned ExtReg = extendRegister(ValVReg, VA);
|
|
|
|
MIRBuilder.buildCopy(PhysReg, ExtReg);
|
|
|
|
}
|
|
|
|
|
|
|
|
void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
|
|
|
|
MachinePointerInfo &MPO, CCValAssign &VA) override {
|
|
|
|
llvm_unreachable("Don't know how to assign a value to an address yet");
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineInstrBuilder &MIB;
|
|
|
|
};
|
|
|
|
} // End anonymous namespace.
|
|
|
|
|
2016-11-15 14:34:33 +08:00
|
|
|
bool X86CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
|
|
|
|
const Value *Val, unsigned VReg) const {
|
|
|
|
|
2017-02-06 16:37:41 +08:00
|
|
|
assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
|
|
|
|
|
|
|
|
auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
|
|
|
|
|
|
|
|
if (VReg) {
|
|
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
auto &DL = MF.getDataLayout();
|
|
|
|
const Function &F = *MF.getFunction();
|
2017-01-29 16:35:42 +08:00
|
|
|
|
2017-02-06 16:37:41 +08:00
|
|
|
ArgInfo OrigArg{VReg, Val->getType()};
|
|
|
|
setArgFlags(OrigArg, AttributeSet::ReturnIndex, DL, F);
|
2016-11-15 14:34:33 +08:00
|
|
|
|
2017-02-06 16:37:41 +08:00
|
|
|
SmallVector<ArgInfo, 8> SplitArgs;
|
|
|
|
splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
|
2017-03-07 07:50:28 +08:00
|
|
|
[&](unsigned Reg, uint64_t Offset) {
|
|
|
|
MIRBuilder.buildExtract(Reg, VReg, Offset);
|
2017-02-06 16:37:41 +08:00
|
|
|
});
|
|
|
|
|
|
|
|
FuncReturnHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
|
|
|
|
if(!handleAssignments(MIRBuilder, SplitArgs, Handler))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
MIRBuilder.insertInstr(MIB);
|
2016-11-15 14:34:33 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-01-29 16:35:42 +08:00
|
|
|
namespace {
|
|
|
|
struct FormalArgHandler : public CallLowering::ValueHandler {
|
|
|
|
FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
|
|
|
|
CCAssignFn *AssignFn, const DataLayout &DL)
|
|
|
|
: ValueHandler(MIRBuilder, MRI, AssignFn), DL(DL) {}
|
|
|
|
|
|
|
|
unsigned getStackAddress(uint64_t Size, int64_t Offset,
|
|
|
|
MachinePointerInfo &MPO) override {
|
|
|
|
|
|
|
|
auto &MFI = MIRBuilder.getMF().getFrameInfo();
|
|
|
|
int FI = MFI.CreateFixedObject(Size, Offset, true);
|
|
|
|
MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
|
|
|
|
|
|
|
|
unsigned AddrReg =
|
|
|
|
MRI.createGenericVirtualRegister(LLT::pointer(0,
|
|
|
|
DL.getPointerSizeInBits(0)));
|
|
|
|
MIRBuilder.buildFrameIndex(AddrReg, FI);
|
|
|
|
return AddrReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
|
|
|
|
MachinePointerInfo &MPO, CCValAssign &VA) override {
|
|
|
|
|
|
|
|
auto MMO = MIRBuilder.getMF().getMachineMemOperand(
|
|
|
|
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
|
|
|
|
0);
|
|
|
|
MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
|
|
|
|
}
|
|
|
|
|
|
|
|
void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
|
|
|
|
CCValAssign &VA) override {
|
|
|
|
MIRBuilder.getMBB().addLiveIn(PhysReg);
|
|
|
|
MIRBuilder.buildCopy(ValVReg, PhysReg);
|
|
|
|
}
|
|
|
|
|
|
|
|
const DataLayout &DL;
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2016-11-15 14:34:33 +08:00
|
|
|
bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
|
|
|
|
const Function &F,
|
|
|
|
ArrayRef<unsigned> VRegs) const {
|
2017-01-29 16:35:42 +08:00
|
|
|
if (F.arg_empty())
|
|
|
|
return true;
|
|
|
|
|
|
|
|
//TODO: handle variadic function
|
|
|
|
if (F.isVarArg())
|
|
|
|
return false;
|
|
|
|
|
2017-02-06 16:37:41 +08:00
|
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
auto DL = MF.getDataLayout();
|
2017-01-29 16:35:42 +08:00
|
|
|
|
2017-02-06 16:37:41 +08:00
|
|
|
SmallVector<ArgInfo, 8> SplitArgs;
|
2017-01-29 16:35:42 +08:00
|
|
|
unsigned Idx = 0;
|
|
|
|
for (auto &Arg : F.getArgumentList()) {
|
2017-02-06 16:37:41 +08:00
|
|
|
ArgInfo OrigArg(VRegs[Idx], Arg.getType());
|
|
|
|
setArgFlags(OrigArg, Idx + 1, DL, F);
|
2017-03-07 07:50:28 +08:00
|
|
|
LLT Ty = MRI.getType(VRegs[Idx]);
|
|
|
|
unsigned Dst = VRegs[Idx];
|
|
|
|
bool Split = false;
|
2017-02-06 16:37:41 +08:00
|
|
|
splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
|
2017-03-07 07:50:28 +08:00
|
|
|
[&](unsigned Reg, uint64_t Offset) {
|
|
|
|
if (!Split) {
|
|
|
|
Split = true;
|
|
|
|
Dst = MRI.createGenericVirtualRegister(Ty);
|
|
|
|
MIRBuilder.buildUndef(Dst);
|
|
|
|
}
|
|
|
|
unsigned Tmp = MRI.createGenericVirtualRegister(Ty);
|
|
|
|
MIRBuilder.buildInsert(Tmp, Dst, Reg, Offset);
|
|
|
|
Dst = Tmp;
|
2017-02-06 16:37:41 +08:00
|
|
|
});
|
2017-03-07 07:50:28 +08:00
|
|
|
if (Dst != VRegs[Idx])
|
|
|
|
MIRBuilder.buildCopy(VRegs[Idx], Dst);
|
2017-01-29 16:35:42 +08:00
|
|
|
Idx++;
|
|
|
|
}
|
|
|
|
|
2017-02-06 16:37:41 +08:00
|
|
|
MachineBasicBlock &MBB = MIRBuilder.getMBB();
|
|
|
|
if (!MBB.empty())
|
|
|
|
MIRBuilder.setInstr(*MBB.begin());
|
|
|
|
|
|
|
|
FormalArgHandler Handler(MIRBuilder, MRI, CC_X86, DL);
|
|
|
|
if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Move back to the end of the basic block.
|
|
|
|
MIRBuilder.setMBB(MBB);
|
|
|
|
|
|
|
|
return true;
|
2016-11-15 14:34:33 +08:00
|
|
|
}
|