2016-01-21 04:58:56 +08:00
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//===-- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator --*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the IRTranslator class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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2017-02-24 07:57:28 +08:00
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#include "llvm/ADT/ScopeExit.h"
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2017-01-18 06:13:50 +08:00
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#include "llvm/ADT/SmallSet.h"
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2016-02-12 03:59:41 +08:00
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#include "llvm/ADT/SmallVector.h"
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2017-02-24 05:05:42 +08:00
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#include "llvm/Analysis/OptimizationDiagnosticInfo.h"
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2016-02-17 03:26:02 +08:00
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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2016-11-10 06:39:54 +08:00
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#include "llvm/CodeGen/Analysis.h"
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2016-02-11 06:59:27 +08:00
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#include "llvm/CodeGen/MachineFunction.h"
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2016-07-23 00:59:52 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2016-11-10 06:39:54 +08:00
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#include "llvm/CodeGen/MachineModuleInfo.h"
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2016-02-12 01:51:31 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2016-08-27 07:49:05 +08:00
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#include "llvm/CodeGen/TargetPassConfig.h"
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2016-02-12 01:51:31 +08:00
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#include "llvm/IR/Constant.h"
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2017-01-27 07:39:14 +08:00
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#include "llvm/IR/DebugInfo.h"
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2016-02-11 06:59:27 +08:00
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#include "llvm/IR/Function.h"
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2016-09-12 19:20:22 +08:00
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#include "llvm/IR/GetElementPtrTypeIterator.h"
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2016-07-30 06:32:36 +08:00
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#include "llvm/IR/IntrinsicInst.h"
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2016-02-12 01:51:31 +08:00
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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2017-02-04 02:22:45 +08:00
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#include "llvm/Target/TargetFrameLowering.h"
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2016-07-30 06:32:36 +08:00
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#include "llvm/Target/TargetIntrinsicInfo.h"
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2016-02-12 02:53:28 +08:00
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#include "llvm/Target/TargetLowering.h"
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2016-02-11 06:59:27 +08:00
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#define DEBUG_TYPE "irtranslator"
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2016-01-21 04:58:56 +08:00
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using namespace llvm;
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char IRTranslator::ID = 0;
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2016-08-27 07:49:05 +08:00
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INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_END(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
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2016-07-26 11:29:18 +08:00
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false, false)
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2016-01-21 04:58:56 +08:00
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2017-02-24 05:05:42 +08:00
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static void reportTranslationError(MachineFunction &MF,
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const TargetPassConfig &TPC,
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OptimizationRemarkEmitter &ORE,
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OptimizationRemarkMissed &R) {
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MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
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// Print the function name explicitly if we don't have a debug location (which
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// makes the diagnostic less useful) or if we're going to emit a raw error.
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if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
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R << (" (in function: " + MF.getName() + ")").str();
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if (TPC.isGlobalISelAbortEnabled())
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report_fatal_error(R.getMsg());
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else
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ORE.emit(R);
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2016-11-08 09:12:17 +08:00
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}
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2016-02-12 01:53:23 +08:00
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IRTranslator::IRTranslator() : MachineFunctionPass(ID), MRI(nullptr) {
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2016-03-08 09:38:55 +08:00
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initializeIRTranslatorPass(*PassRegistry::getPassRegistry());
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2016-02-12 01:53:23 +08:00
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}
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2016-08-27 07:49:05 +08:00
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void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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2016-03-12 01:27:54 +08:00
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unsigned IRTranslator::getOrCreateVReg(const Value &Val) {
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unsigned &ValReg = ValToVReg[&Val];
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2017-01-26 04:58:22 +08:00
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if (ValReg)
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return ValReg;
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// Fill ValRegsSequence with the sequence of registers
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// we need to concat together to produce the value.
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assert(Val.getType()->isSized() &&
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"Don't know how to create an empty vreg");
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2017-03-08 03:21:23 +08:00
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unsigned VReg = MRI->createGenericVirtualRegister(LLT{*Val.getType(), *DL});
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2017-01-26 04:58:22 +08:00
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ValReg = VReg;
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if (auto CV = dyn_cast<Constant>(&Val)) {
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bool Success = translate(*CV, VReg);
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if (!Success) {
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2017-02-24 05:05:42 +08:00
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OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
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2017-02-24 08:34:44 +08:00
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MF->getFunction()->getSubprogram(),
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2017-02-24 05:05:42 +08:00
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&MF->getFunction()->getEntryBlock());
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R << "unable to translate constant: " << ore::NV("Type", Val.getType());
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reportTranslationError(*MF, *TPC, *ORE, R);
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return VReg;
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2016-08-10 05:28:04 +08:00
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}
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2016-02-12 01:51:31 +08:00
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}
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2017-01-21 07:25:17 +08:00
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2017-01-26 04:58:22 +08:00
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return VReg;
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2016-02-12 01:51:31 +08:00
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}
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2016-11-01 02:30:59 +08:00
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int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
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if (FrameIndices.find(&AI) != FrameIndices.end())
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return FrameIndices[&AI];
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unsigned ElementSize = DL->getTypeStoreSize(AI.getAllocatedType());
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unsigned Size =
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ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
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// Always allocate at least one byte.
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Size = std::max(Size, 1u);
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unsigned Alignment = AI.getAlignment();
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if (!Alignment)
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Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
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int &FI = FrameIndices[&AI];
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2016-12-08 05:17:47 +08:00
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FI = MF->getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
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2016-11-01 02:30:59 +08:00
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return FI;
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}
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2016-07-27 04:23:26 +08:00
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unsigned IRTranslator::getMemOpAlignment(const Instruction &I) {
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unsigned Alignment = 0;
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Type *ValTy = nullptr;
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if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) {
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Alignment = SI->getAlignment();
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ValTy = SI->getValueOperand()->getType();
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} else if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) {
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Alignment = LI->getAlignment();
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ValTy = LI->getType();
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2017-02-24 05:05:42 +08:00
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} else {
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OptimizationRemarkMissed R("gisel-irtranslator", "", &I);
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R << "unable to translate memop: " << ore::NV("Opcode", &I);
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reportTranslationError(*MF, *TPC, *ORE, R);
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2016-08-27 07:49:05 +08:00
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return 1;
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2017-02-24 05:05:42 +08:00
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}
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2016-07-27 04:23:26 +08:00
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return Alignment ? Alignment : DL->getABITypeAlignment(ValTy);
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}
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2016-03-12 01:27:43 +08:00
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MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock &BB) {
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MachineBasicBlock *&MBB = BBToMBB[&BB];
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2016-02-12 01:51:31 +08:00
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if (!MBB) {
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2017-01-05 21:27:52 +08:00
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MBB = MF->CreateMachineBasicBlock(&BB);
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2016-12-08 05:17:47 +08:00
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MF->push_back(MBB);
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2017-01-05 21:27:52 +08:00
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if (BB.hasAddressTaken())
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MBB->setHasAddressTaken();
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2016-02-12 01:51:31 +08:00
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}
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return *MBB;
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}
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2017-01-18 06:13:50 +08:00
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void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
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assert(NewPred && "new predecessor must be a real MachineBasicBlock");
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MachinePreds[Edge].push_back(NewPred);
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}
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2016-12-08 05:29:15 +08:00
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bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
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MachineIRBuilder &MIRBuilder) {
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2016-07-30 02:11:21 +08:00
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// FIXME: handle signed/unsigned wrapping flags.
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2016-02-11 06:59:27 +08:00
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// Get or create a virtual register for each value.
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// Unless the value is a Constant => loadimm cst?
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// or inline constant each time?
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// Creation of a virtual register needs to have a size.
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2016-08-11 07:02:41 +08:00
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unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
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unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
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unsigned Res = getOrCreateVReg(U);
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2016-09-09 19:46:34 +08:00
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MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1);
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2016-02-12 01:51:31 +08:00
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return true;
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2016-01-21 04:58:56 +08:00
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}
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2017-03-08 02:03:28 +08:00
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bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
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// -0.0 - X --> G_FNEG
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if (isa<Constant>(U.getOperand(0)) &&
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U.getOperand(0) == ConstantFP::getZeroValueForNegation(U.getType())) {
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MIRBuilder.buildInstr(TargetOpcode::G_FNEG)
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.addDef(getOrCreateVReg(U))
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.addUse(getOrCreateVReg(*U.getOperand(1)));
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return true;
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}
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return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
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}
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2016-12-08 05:29:15 +08:00
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bool IRTranslator::translateCompare(const User &U,
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MachineIRBuilder &MIRBuilder) {
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2016-08-20 04:48:16 +08:00
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const CmpInst *CI = dyn_cast<CmpInst>(&U);
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unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
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unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
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unsigned Res = getOrCreateVReg(U);
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CmpInst::Predicate Pred =
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CI ? CI->getPredicate() : static_cast<CmpInst::Predicate>(
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cast<ConstantExpr>(U).getPredicate());
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if (CmpInst::isIntPredicate(Pred))
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2016-09-09 19:46:34 +08:00
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MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
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2016-08-20 04:48:16 +08:00
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else
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2016-09-09 19:46:34 +08:00
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MIRBuilder.buildFCmp(Pred, Res, Op0, Op1);
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2016-08-20 04:48:16 +08:00
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2016-08-18 04:25:25 +08:00
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return true;
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}
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2016-12-08 05:29:15 +08:00
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bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
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2016-08-11 07:02:41 +08:00
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const ReturnInst &RI = cast<ReturnInst>(U);
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2016-07-30 02:11:21 +08:00
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const Value *Ret = RI.getReturnValue();
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2016-02-12 02:53:28 +08:00
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// The target may mess up with the insertion point, but
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// this is not important as a return is the last instruction
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// of the block anyway.
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2016-04-15 01:23:33 +08:00
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return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
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2016-02-12 02:53:28 +08:00
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}
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2016-12-08 05:29:15 +08:00
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bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
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2016-08-11 07:02:41 +08:00
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const BranchInst &BrInst = cast<BranchInst>(U);
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2016-07-30 01:58:00 +08:00
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unsigned Succ = 0;
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if (!BrInst.isUnconditional()) {
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// We want a G_BRCOND to the true BB followed by an unconditional branch.
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unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
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const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
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MachineBasicBlock &TrueBB = getOrCreateBB(TrueTgt);
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2016-09-09 19:46:34 +08:00
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MIRBuilder.buildBrCond(Tst, TrueBB);
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2016-03-12 01:28:03 +08:00
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}
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2016-07-30 01:58:00 +08:00
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const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
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MachineBasicBlock &TgtBB = getOrCreateBB(BrTgt);
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MIRBuilder.buildBr(TgtBB);
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2016-03-12 01:28:03 +08:00
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// Link successors.
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MachineBasicBlock &CurBB = MIRBuilder.getMBB();
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for (const BasicBlock *Succ : BrInst.successors())
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CurBB.addSuccessor(&getOrCreateBB(*Succ));
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return true;
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}
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2017-01-05 19:28:51 +08:00
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bool IRTranslator::translateSwitch(const User &U,
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MachineIRBuilder &MIRBuilder) {
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// For now, just translate as a chain of conditional branches.
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// FIXME: could we share most of the logic/code in
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// SelectionDAGBuilder::visitSwitch between SelectionDAG and GlobalISel?
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// At first sight, it seems most of the logic in there is independent of
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// SelectionDAG-specifics and a lot of work went in to optimize switch
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// lowering in there.
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const SwitchInst &SwInst = cast<SwitchInst>(U);
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const unsigned SwCondValue = getOrCreateVReg(*SwInst.getCondition());
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2017-01-18 06:13:50 +08:00
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const BasicBlock *OrigBB = SwInst.getParent();
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2017-01-05 19:28:51 +08:00
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2017-03-08 03:21:23 +08:00
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LLT LLTi1 = LLT(*Type::getInt1Ty(U.getContext()), *DL);
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2017-01-05 19:28:51 +08:00
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for (auto &CaseIt : SwInst.cases()) {
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const unsigned CaseValueReg = getOrCreateVReg(*CaseIt.getCaseValue());
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const unsigned Tst = MRI->createGenericVirtualRegister(LLTi1);
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MIRBuilder.buildICmp(CmpInst::ICMP_EQ, Tst, CaseValueReg, SwCondValue);
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2017-01-18 06:13:50 +08:00
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MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
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const BasicBlock *TrueBB = CaseIt.getCaseSuccessor();
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MachineBasicBlock &TrueMBB = getOrCreateBB(*TrueBB);
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2017-01-05 19:28:51 +08:00
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2017-01-18 06:13:50 +08:00
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MIRBuilder.buildBrCond(Tst, TrueMBB);
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CurMBB.addSuccessor(&TrueMBB);
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addMachineCFGPred({OrigBB, TrueBB}, &CurMBB);
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2017-01-05 19:28:51 +08:00
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2017-01-18 06:13:50 +08:00
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MachineBasicBlock *FalseMBB =
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2017-01-05 19:28:51 +08:00
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MF->CreateMachineBasicBlock(SwInst.getParent());
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2017-01-18 06:13:50 +08:00
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MF->push_back(FalseMBB);
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MIRBuilder.buildBr(*FalseMBB);
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CurMBB.addSuccessor(FalseMBB);
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2017-01-05 19:28:51 +08:00
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2017-01-18 06:13:50 +08:00
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MIRBuilder.setMBB(*FalseMBB);
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2017-01-05 19:28:51 +08:00
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}
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// handle default case
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2017-01-18 06:13:50 +08:00
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const BasicBlock *DefaultBB = SwInst.getDefaultDest();
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MachineBasicBlock &DefaultMBB = getOrCreateBB(*DefaultBB);
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MIRBuilder.buildBr(DefaultMBB);
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MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
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CurMBB.addSuccessor(&DefaultMBB);
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|
|
addMachineCFGPred({OrigBB, DefaultBB}, &CurMBB);
|
2017-01-05 19:28:51 +08:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-01-30 17:13:18 +08:00
|
|
|
bool IRTranslator::translateIndirectBr(const User &U,
|
|
|
|
MachineIRBuilder &MIRBuilder) {
|
|
|
|
const IndirectBrInst &BrInst = cast<IndirectBrInst>(U);
|
|
|
|
|
|
|
|
const unsigned Tgt = getOrCreateVReg(*BrInst.getAddress());
|
|
|
|
MIRBuilder.buildBrIndirect(Tgt);
|
|
|
|
|
|
|
|
// Link successors.
|
|
|
|
MachineBasicBlock &CurBB = MIRBuilder.getMBB();
|
|
|
|
for (const BasicBlock *Succ : BrInst.successors())
|
|
|
|
CurBB.addSuccessor(&getOrCreateBB(*Succ));
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
|
2016-08-11 07:02:41 +08:00
|
|
|
const LoadInst &LI = cast<LoadInst>(U);
|
2016-08-27 07:49:05 +08:00
|
|
|
|
2016-10-19 23:55:06 +08:00
|
|
|
auto Flags = LI.isVolatile() ? MachineMemOperand::MOVolatile
|
|
|
|
: MachineMemOperand::MONone;
|
|
|
|
Flags |= MachineMemOperand::MOLoad;
|
2016-07-27 04:23:26 +08:00
|
|
|
|
|
|
|
unsigned Res = getOrCreateVReg(LI);
|
|
|
|
unsigned Addr = getOrCreateVReg(*LI.getPointerOperand());
|
2017-03-08 03:21:23 +08:00
|
|
|
LLT VTy{*LI.getType(), *DL}, PTy{*LI.getPointerOperand()->getType(), *DL};
|
2016-07-27 04:23:26 +08:00
|
|
|
MIRBuilder.buildLoad(
|
2016-09-09 19:46:34 +08:00
|
|
|
Res, Addr,
|
2016-12-08 05:17:47 +08:00
|
|
|
*MF->getMachineMemOperand(MachinePointerInfo(LI.getPointerOperand()),
|
|
|
|
Flags, DL->getTypeStoreSize(LI.getType()),
|
2017-02-14 06:14:16 +08:00
|
|
|
getMemOpAlignment(LI), AAMDNodes(), nullptr,
|
|
|
|
LI.getSynchScope(), LI.getOrdering()));
|
2016-07-27 04:23:26 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
|
2016-08-11 07:02:41 +08:00
|
|
|
const StoreInst &SI = cast<StoreInst>(U);
|
2016-10-19 23:55:06 +08:00
|
|
|
auto Flags = SI.isVolatile() ? MachineMemOperand::MOVolatile
|
|
|
|
: MachineMemOperand::MONone;
|
|
|
|
Flags |= MachineMemOperand::MOStore;
|
2016-07-27 04:23:26 +08:00
|
|
|
|
|
|
|
unsigned Val = getOrCreateVReg(*SI.getValueOperand());
|
|
|
|
unsigned Addr = getOrCreateVReg(*SI.getPointerOperand());
|
2017-03-08 03:21:23 +08:00
|
|
|
LLT VTy{*SI.getValueOperand()->getType(), *DL},
|
|
|
|
PTy{*SI.getPointerOperand()->getType(), *DL};
|
2016-07-27 04:23:26 +08:00
|
|
|
|
|
|
|
MIRBuilder.buildStore(
|
2016-12-08 05:17:47 +08:00
|
|
|
Val, Addr,
|
|
|
|
*MF->getMachineMemOperand(
|
|
|
|
MachinePointerInfo(SI.getPointerOperand()), Flags,
|
|
|
|
DL->getTypeStoreSize(SI.getValueOperand()->getType()),
|
2017-02-14 06:14:16 +08:00
|
|
|
getMemOpAlignment(SI), AAMDNodes(), nullptr, SI.getSynchScope(),
|
|
|
|
SI.getOrdering()));
|
2016-07-27 04:23:26 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
bool IRTranslator::translateExtractValue(const User &U,
|
|
|
|
MachineIRBuilder &MIRBuilder) {
|
2016-08-20 04:09:03 +08:00
|
|
|
const Value *Src = U.getOperand(0);
|
|
|
|
Type *Int32Ty = Type::getInt32Ty(U.getContext());
|
2016-08-20 01:47:05 +08:00
|
|
|
SmallVector<Value *, 1> Indices;
|
|
|
|
|
|
|
|
// getIndexedOffsetInType is designed for GEPs, so the first index is the
|
|
|
|
// usual array element rather than looking into the actual aggregate.
|
|
|
|
Indices.push_back(ConstantInt::get(Int32Ty, 0));
|
2016-08-20 04:09:03 +08:00
|
|
|
|
|
|
|
if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&U)) {
|
|
|
|
for (auto Idx : EVI->indices())
|
|
|
|
Indices.push_back(ConstantInt::get(Int32Ty, Idx));
|
|
|
|
} else {
|
|
|
|
for (unsigned i = 1; i < U.getNumOperands(); ++i)
|
|
|
|
Indices.push_back(U.getOperand(i));
|
|
|
|
}
|
2016-08-20 01:47:05 +08:00
|
|
|
|
|
|
|
uint64_t Offset = 8 * DL->getIndexedOffsetInType(Src->getType(), Indices);
|
|
|
|
|
2016-08-20 04:09:03 +08:00
|
|
|
unsigned Res = getOrCreateVReg(U);
|
2017-03-07 07:50:28 +08:00
|
|
|
MIRBuilder.buildExtract(Res, getOrCreateVReg(*Src), Offset);
|
2016-08-20 01:47:05 +08:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
bool IRTranslator::translateInsertValue(const User &U,
|
|
|
|
MachineIRBuilder &MIRBuilder) {
|
2016-08-20 04:09:03 +08:00
|
|
|
const Value *Src = U.getOperand(0);
|
|
|
|
Type *Int32Ty = Type::getInt32Ty(U.getContext());
|
2016-08-20 04:08:55 +08:00
|
|
|
SmallVector<Value *, 1> Indices;
|
|
|
|
|
|
|
|
// getIndexedOffsetInType is designed for GEPs, so the first index is the
|
|
|
|
// usual array element rather than looking into the actual aggregate.
|
|
|
|
Indices.push_back(ConstantInt::get(Int32Ty, 0));
|
2016-08-20 04:09:03 +08:00
|
|
|
|
|
|
|
if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(&U)) {
|
|
|
|
for (auto Idx : IVI->indices())
|
|
|
|
Indices.push_back(ConstantInt::get(Int32Ty, Idx));
|
|
|
|
} else {
|
|
|
|
for (unsigned i = 2; i < U.getNumOperands(); ++i)
|
|
|
|
Indices.push_back(U.getOperand(i));
|
|
|
|
}
|
2016-08-20 04:08:55 +08:00
|
|
|
|
|
|
|
uint64_t Offset = 8 * DL->getIndexedOffsetInType(Src->getType(), Indices);
|
|
|
|
|
2016-08-20 04:09:03 +08:00
|
|
|
unsigned Res = getOrCreateVReg(U);
|
|
|
|
const Value &Inserted = *U.getOperand(1);
|
2016-09-09 19:46:34 +08:00
|
|
|
MIRBuilder.buildInsert(Res, getOrCreateVReg(*Src), getOrCreateVReg(Inserted),
|
|
|
|
Offset);
|
2016-08-20 04:08:55 +08:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
bool IRTranslator::translateSelect(const User &U,
|
|
|
|
MachineIRBuilder &MIRBuilder) {
|
2016-09-09 19:46:34 +08:00
|
|
|
MIRBuilder.buildSelect(getOrCreateVReg(U), getOrCreateVReg(*U.getOperand(0)),
|
|
|
|
getOrCreateVReg(*U.getOperand(1)),
|
|
|
|
getOrCreateVReg(*U.getOperand(2)));
|
2016-08-20 04:09:07 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
bool IRTranslator::translateBitCast(const User &U,
|
|
|
|
MachineIRBuilder &MIRBuilder) {
|
2017-03-08 04:53:06 +08:00
|
|
|
// If we're bitcasting to the source type, we can reuse the source vreg.
|
2017-03-08 03:21:23 +08:00
|
|
|
if (LLT{*U.getOperand(0)->getType(), *DL} == LLT{*U.getType(), *DL}) {
|
2017-03-08 04:53:06 +08:00
|
|
|
// Get the source vreg now, to avoid invalidating ValToVReg.
|
|
|
|
unsigned SrcReg = getOrCreateVReg(*U.getOperand(0));
|
2016-08-11 07:02:41 +08:00
|
|
|
unsigned &Reg = ValToVReg[&U];
|
2017-03-08 04:53:06 +08:00
|
|
|
// If we already assigned a vreg for this bitcast, we can't change that.
|
|
|
|
// Emit a copy to satisfy the users we already emitted.
|
2016-08-11 00:51:14 +08:00
|
|
|
if (Reg)
|
2017-03-08 04:53:06 +08:00
|
|
|
MIRBuilder.buildCopy(Reg, SrcReg);
|
2016-08-11 00:51:14 +08:00
|
|
|
else
|
2017-03-08 04:53:06 +08:00
|
|
|
Reg = SrcReg;
|
2016-07-26 05:01:29 +08:00
|
|
|
return true;
|
|
|
|
}
|
2016-12-08 05:29:15 +08:00
|
|
|
return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
|
2016-07-26 05:01:29 +08:00
|
|
|
}
|
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
bool IRTranslator::translateCast(unsigned Opcode, const User &U,
|
|
|
|
MachineIRBuilder &MIRBuilder) {
|
2016-08-11 07:02:41 +08:00
|
|
|
unsigned Op = getOrCreateVReg(*U.getOperand(0));
|
|
|
|
unsigned Res = getOrCreateVReg(U);
|
2016-09-09 19:46:34 +08:00
|
|
|
MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op);
|
2016-07-26 05:01:29 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
bool IRTranslator::translateGetElementPtr(const User &U,
|
|
|
|
MachineIRBuilder &MIRBuilder) {
|
2016-09-12 19:20:22 +08:00
|
|
|
// FIXME: support vector GEPs.
|
|
|
|
if (U.getType()->isVectorTy())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
Value &Op0 = *U.getOperand(0);
|
|
|
|
unsigned BaseReg = getOrCreateVReg(Op0);
|
2017-03-08 03:21:23 +08:00
|
|
|
LLT PtrTy{*Op0.getType(), *DL};
|
2016-09-12 19:20:22 +08:00
|
|
|
unsigned PtrSize = DL->getPointerSizeInBits(PtrTy.getAddressSpace());
|
|
|
|
LLT OffsetTy = LLT::scalar(PtrSize);
|
|
|
|
|
|
|
|
int64_t Offset = 0;
|
|
|
|
for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
|
|
|
|
GTI != E; ++GTI) {
|
|
|
|
const Value *Idx = GTI.getOperand();
|
2016-12-02 10:55:30 +08:00
|
|
|
if (StructType *StTy = GTI.getStructTypeOrNull()) {
|
2016-09-12 19:20:22 +08:00
|
|
|
unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
|
|
|
|
Offset += DL->getStructLayout(StTy)->getElementOffset(Field);
|
|
|
|
continue;
|
|
|
|
} else {
|
|
|
|
uint64_t ElementSize = DL->getTypeAllocSize(GTI.getIndexedType());
|
|
|
|
|
|
|
|
// If this is a scalar constant or a splat vector of constants,
|
|
|
|
// handle it quickly.
|
|
|
|
if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
|
|
|
|
Offset += ElementSize * CI->getSExtValue();
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Offset != 0) {
|
|
|
|
unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
|
|
|
|
unsigned OffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
|
|
|
|
MIRBuilder.buildConstant(OffsetReg, Offset);
|
|
|
|
MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
|
|
|
|
|
|
|
|
BaseReg = NewBaseReg;
|
|
|
|
Offset = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// N = N + Idx * ElementSize;
|
|
|
|
unsigned ElementSizeReg = MRI->createGenericVirtualRegister(OffsetTy);
|
|
|
|
MIRBuilder.buildConstant(ElementSizeReg, ElementSize);
|
|
|
|
|
|
|
|
unsigned IdxReg = getOrCreateVReg(*Idx);
|
|
|
|
if (MRI->getType(IdxReg) != OffsetTy) {
|
|
|
|
unsigned NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
|
|
|
|
MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
|
|
|
|
IdxReg = NewIdxReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned OffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
|
|
|
|
MIRBuilder.buildMul(OffsetReg, ElementSizeReg, IdxReg);
|
|
|
|
|
|
|
|
unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
|
|
|
|
MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
|
|
|
|
BaseReg = NewBaseReg;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Offset != 0) {
|
|
|
|
unsigned OffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
|
|
|
|
MIRBuilder.buildConstant(OffsetReg, Offset);
|
|
|
|
MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-01-31 03:33:07 +08:00
|
|
|
bool IRTranslator::translateMemfunc(const CallInst &CI,
|
|
|
|
MachineIRBuilder &MIRBuilder,
|
|
|
|
unsigned ID) {
|
2017-03-08 03:21:23 +08:00
|
|
|
LLT SizeTy{*CI.getArgOperand(2)->getType(), *DL};
|
2017-01-31 03:33:07 +08:00
|
|
|
Type *DstTy = CI.getArgOperand(0)->getType();
|
|
|
|
if (cast<PointerType>(DstTy)->getAddressSpace() != 0 ||
|
2016-10-19 04:03:45 +08:00
|
|
|
SizeTy.getSizeInBits() != DL->getPointerSizeInBits(0))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SmallVector<CallLowering::ArgInfo, 8> Args;
|
|
|
|
for (int i = 0; i < 3; ++i) {
|
|
|
|
const auto &Arg = CI.getArgOperand(i);
|
|
|
|
Args.emplace_back(getOrCreateVReg(*Arg), Arg->getType());
|
|
|
|
}
|
|
|
|
|
2017-01-31 03:33:07 +08:00
|
|
|
const char *Callee;
|
|
|
|
switch (ID) {
|
|
|
|
case Intrinsic::memmove:
|
|
|
|
case Intrinsic::memcpy: {
|
|
|
|
Type *SrcTy = CI.getArgOperand(1)->getType();
|
|
|
|
if(cast<PointerType>(SrcTy)->getAddressSpace() != 0)
|
|
|
|
return false;
|
|
|
|
Callee = ID == Intrinsic::memcpy ? "memcpy" : "memmove";
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case Intrinsic::memset:
|
|
|
|
Callee = "memset";
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
2016-10-19 04:03:45 +08:00
|
|
|
|
2017-01-31 03:33:07 +08:00
|
|
|
return CLI->lowerCall(MIRBuilder, MachineOperand::CreateES(Callee),
|
2016-10-19 04:03:45 +08:00
|
|
|
CallLowering::ArgInfo(0, CI.getType()), Args);
|
|
|
|
}
|
2016-09-12 19:20:22 +08:00
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
void IRTranslator::getStackGuard(unsigned DstReg,
|
|
|
|
MachineIRBuilder &MIRBuilder) {
|
2017-01-28 05:31:24 +08:00
|
|
|
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
|
|
|
|
MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
|
2016-11-01 02:30:59 +08:00
|
|
|
auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
|
|
|
|
MIB.addDef(DstReg);
|
|
|
|
|
2016-12-08 05:17:47 +08:00
|
|
|
auto &TLI = *MF->getSubtarget().getTargetLowering();
|
|
|
|
Value *Global = TLI.getSDagStackGuard(*MF->getFunction()->getParent());
|
2016-11-01 02:30:59 +08:00
|
|
|
if (!Global)
|
|
|
|
return;
|
|
|
|
|
|
|
|
MachinePointerInfo MPInfo(Global);
|
2016-12-08 05:17:47 +08:00
|
|
|
MachineInstr::mmo_iterator MemRefs = MF->allocateMemRefsArray(1);
|
2016-11-01 02:30:59 +08:00
|
|
|
auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
|
|
|
|
MachineMemOperand::MODereferenceable;
|
|
|
|
*MemRefs =
|
2016-12-08 05:17:47 +08:00
|
|
|
MF->getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8,
|
|
|
|
DL->getPointerABIAlignment());
|
2016-11-01 02:30:59 +08:00
|
|
|
MIB.setMemRefs(MemRefs, MemRefs + 1);
|
|
|
|
}
|
|
|
|
|
2016-12-09 06:44:00 +08:00
|
|
|
bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
|
|
|
|
MachineIRBuilder &MIRBuilder) {
|
2017-03-08 03:21:23 +08:00
|
|
|
LLT Ty{*CI.getOperand(0)->getType(), *DL};
|
2016-12-09 06:44:00 +08:00
|
|
|
LLT s1 = LLT::scalar(1);
|
|
|
|
unsigned Width = Ty.getSizeInBits();
|
|
|
|
unsigned Res = MRI->createGenericVirtualRegister(Ty);
|
|
|
|
unsigned Overflow = MRI->createGenericVirtualRegister(s1);
|
|
|
|
auto MIB = MIRBuilder.buildInstr(Op)
|
|
|
|
.addDef(Res)
|
|
|
|
.addDef(Overflow)
|
|
|
|
.addUse(getOrCreateVReg(*CI.getOperand(0)))
|
|
|
|
.addUse(getOrCreateVReg(*CI.getOperand(1)));
|
|
|
|
|
|
|
|
if (Op == TargetOpcode::G_UADDE || Op == TargetOpcode::G_USUBE) {
|
|
|
|
unsigned Zero = MRI->createGenericVirtualRegister(s1);
|
|
|
|
EntryBuilder.buildConstant(Zero, 0);
|
|
|
|
MIB.addUse(Zero);
|
|
|
|
}
|
|
|
|
|
|
|
|
MIRBuilder.buildSequence(getOrCreateVReg(CI), Res, 0, Overflow, Width);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
|
|
|
|
MachineIRBuilder &MIRBuilder) {
|
2016-08-20 01:17:06 +08:00
|
|
|
switch (ID) {
|
2016-12-09 06:44:00 +08:00
|
|
|
default:
|
|
|
|
break;
|
2017-02-11 03:10:38 +08:00
|
|
|
case Intrinsic::lifetime_start:
|
|
|
|
case Intrinsic::lifetime_end:
|
|
|
|
// Stack coloring is not enabled in O0 (which we care about now) so we can
|
|
|
|
// drop these. Make sure someone notices when we start compiling at higher
|
|
|
|
// opts though.
|
|
|
|
if (MF->getTarget().getOptLevel() != CodeGenOpt::None)
|
|
|
|
return false;
|
|
|
|
return true;
|
2017-01-27 07:39:14 +08:00
|
|
|
case Intrinsic::dbg_declare: {
|
|
|
|
const DbgDeclareInst &DI = cast<DbgDeclareInst>(CI);
|
|
|
|
assert(DI.getVariable() && "Missing variable");
|
|
|
|
|
|
|
|
const Value *Address = DI.getAddress();
|
|
|
|
if (!Address || isa<UndefValue>(Address)) {
|
|
|
|
DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned Reg = getOrCreateVReg(*Address);
|
|
|
|
auto RegDef = MRI->def_instr_begin(Reg);
|
|
|
|
assert(DI.getVariable()->isValidLocationForIntrinsic(
|
|
|
|
MIRBuilder.getDebugLoc()) &&
|
|
|
|
"Expected inlined-at fields to agree");
|
|
|
|
|
|
|
|
if (RegDef != MRI->def_instr_end() &&
|
|
|
|
RegDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) {
|
|
|
|
MIRBuilder.buildFIDbgValue(RegDef->getOperand(1).getIndex(),
|
|
|
|
DI.getVariable(), DI.getExpression());
|
|
|
|
} else
|
|
|
|
MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression());
|
2016-12-09 06:44:13 +08:00
|
|
|
return true;
|
2017-01-27 07:39:14 +08:00
|
|
|
}
|
2017-02-08 04:08:59 +08:00
|
|
|
case Intrinsic::vaend:
|
|
|
|
// No target I know of cares about va_end. Certainly no in-tree target
|
|
|
|
// does. Simplest intrinsic ever!
|
|
|
|
return true;
|
2017-02-09 01:57:20 +08:00
|
|
|
case Intrinsic::vastart: {
|
|
|
|
auto &TLI = *MF->getSubtarget().getTargetLowering();
|
|
|
|
Value *Ptr = CI.getArgOperand(0);
|
|
|
|
unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8;
|
|
|
|
|
|
|
|
MIRBuilder.buildInstr(TargetOpcode::G_VASTART)
|
|
|
|
.addUse(getOrCreateVReg(*Ptr))
|
|
|
|
.addMemOperand(MF->getMachineMemOperand(
|
|
|
|
MachinePointerInfo(Ptr), MachineMemOperand::MOStore, ListSize, 0));
|
|
|
|
return true;
|
|
|
|
}
|
2017-01-27 07:39:14 +08:00
|
|
|
case Intrinsic::dbg_value: {
|
|
|
|
// This form of DBG_VALUE is target-independent.
|
|
|
|
const DbgValueInst &DI = cast<DbgValueInst>(CI);
|
|
|
|
const Value *V = DI.getValue();
|
|
|
|
assert(DI.getVariable()->isValidLocationForIntrinsic(
|
|
|
|
MIRBuilder.getDebugLoc()) &&
|
|
|
|
"Expected inlined-at fields to agree");
|
|
|
|
if (!V) {
|
|
|
|
// Currently the optimizer can produce this; insert an undef to
|
|
|
|
// help debugging. Probably the optimizer should not do this.
|
|
|
|
MIRBuilder.buildIndirectDbgValue(0, DI.getOffset(), DI.getVariable(),
|
|
|
|
DI.getExpression());
|
|
|
|
} else if (const auto *CI = dyn_cast<Constant>(V)) {
|
|
|
|
MIRBuilder.buildConstDbgValue(*CI, DI.getOffset(), DI.getVariable(),
|
|
|
|
DI.getExpression());
|
|
|
|
} else {
|
|
|
|
unsigned Reg = getOrCreateVReg(*V);
|
|
|
|
// FIXME: This does not handle register-indirect values at offset 0. The
|
|
|
|
// direct/indirect thing shouldn't really be handled by something as
|
|
|
|
// implicit as reg+noreg vs reg+imm in the first palce, but it seems
|
|
|
|
// pretty baked in right now.
|
|
|
|
if (DI.getOffset() != 0)
|
|
|
|
MIRBuilder.buildIndirectDbgValue(Reg, DI.getOffset(), DI.getVariable(),
|
|
|
|
DI.getExpression());
|
|
|
|
else
|
|
|
|
MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(),
|
|
|
|
DI.getExpression());
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
2016-12-09 06:44:00 +08:00
|
|
|
case Intrinsic::uadd_with_overflow:
|
|
|
|
return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDE, MIRBuilder);
|
|
|
|
case Intrinsic::sadd_with_overflow:
|
|
|
|
return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
|
|
|
|
case Intrinsic::usub_with_overflow:
|
|
|
|
return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBE, MIRBuilder);
|
|
|
|
case Intrinsic::ssub_with_overflow:
|
|
|
|
return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
|
|
|
|
case Intrinsic::umul_with_overflow:
|
|
|
|
return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
|
|
|
|
case Intrinsic::smul_with_overflow:
|
|
|
|
return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
|
2017-02-09 07:23:32 +08:00
|
|
|
case Intrinsic::pow:
|
|
|
|
MIRBuilder.buildInstr(TargetOpcode::G_FPOW)
|
|
|
|
.addDef(getOrCreateVReg(CI))
|
|
|
|
.addUse(getOrCreateVReg(*CI.getArgOperand(0)))
|
|
|
|
.addUse(getOrCreateVReg(*CI.getArgOperand(1)));
|
|
|
|
return true;
|
2016-10-19 04:03:45 +08:00
|
|
|
case Intrinsic::memcpy:
|
2017-01-31 03:33:07 +08:00
|
|
|
case Intrinsic::memmove:
|
|
|
|
case Intrinsic::memset:
|
|
|
|
return translateMemfunc(CI, MIRBuilder, ID);
|
2016-11-10 06:39:54 +08:00
|
|
|
case Intrinsic::eh_typeid_for: {
|
|
|
|
GlobalValue *GV = ExtractTypeInfo(CI.getArgOperand(0));
|
|
|
|
unsigned Reg = getOrCreateVReg(CI);
|
2016-12-08 05:17:47 +08:00
|
|
|
unsigned TypeID = MF->getTypeIDFor(GV);
|
2016-11-10 06:39:54 +08:00
|
|
|
MIRBuilder.buildConstant(Reg, TypeID);
|
|
|
|
return true;
|
|
|
|
}
|
2016-10-19 04:03:51 +08:00
|
|
|
case Intrinsic::objectsize: {
|
|
|
|
// If we don't know by now, we're never going to know.
|
|
|
|
const ConstantInt *Min = cast<ConstantInt>(CI.getArgOperand(1));
|
|
|
|
|
|
|
|
MIRBuilder.buildConstant(getOrCreateVReg(CI), Min->isZero() ? -1ULL : 0);
|
|
|
|
return true;
|
|
|
|
}
|
2016-11-01 02:30:59 +08:00
|
|
|
case Intrinsic::stackguard:
|
2016-12-08 05:29:15 +08:00
|
|
|
getStackGuard(getOrCreateVReg(CI), MIRBuilder);
|
2016-11-01 02:30:59 +08:00
|
|
|
return true;
|
|
|
|
case Intrinsic::stackprotector: {
|
2017-03-08 03:21:23 +08:00
|
|
|
LLT PtrTy{*CI.getArgOperand(0)->getType(), *DL};
|
2016-11-01 02:30:59 +08:00
|
|
|
unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
|
2016-12-08 05:29:15 +08:00
|
|
|
getStackGuard(GuardVal, MIRBuilder);
|
2016-11-01 02:30:59 +08:00
|
|
|
|
|
|
|
AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
|
|
|
|
MIRBuilder.buildStore(
|
|
|
|
GuardVal, getOrCreateVReg(*Slot),
|
2016-12-08 05:17:47 +08:00
|
|
|
*MF->getMachineMemOperand(
|
|
|
|
MachinePointerInfo::getFixedStack(*MF,
|
|
|
|
getOrCreateFrameIndex(*Slot)),
|
2016-11-01 02:30:59 +08:00
|
|
|
MachineMemOperand::MOStore | MachineMemOperand::MOVolatile,
|
|
|
|
PtrTy.getSizeInBits() / 8, 8));
|
|
|
|
return true;
|
|
|
|
}
|
2016-08-20 01:17:06 +08:00
|
|
|
}
|
2016-12-09 06:44:00 +08:00
|
|
|
return false;
|
2016-08-20 01:17:06 +08:00
|
|
|
}
|
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
|
2016-08-11 07:02:41 +08:00
|
|
|
const CallInst &CI = cast<CallInst>(U);
|
2016-12-08 05:17:47 +08:00
|
|
|
auto TII = MF->getTarget().getIntrinsicInfo();
|
2016-08-11 05:44:01 +08:00
|
|
|
const Function *F = CI.getCalledFunction();
|
|
|
|
|
2017-01-20 07:59:35 +08:00
|
|
|
if (CI.isInlineAsm())
|
|
|
|
return false;
|
|
|
|
|
2016-08-11 05:44:01 +08:00
|
|
|
if (!F || !F->isIntrinsic()) {
|
|
|
|
unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
|
|
|
|
SmallVector<unsigned, 8> Args;
|
|
|
|
for (auto &Arg: CI.arg_operands())
|
|
|
|
Args.push_back(getOrCreateVReg(*Arg));
|
|
|
|
|
2016-08-30 03:07:08 +08:00
|
|
|
return CLI->lowerCall(MIRBuilder, CI, Res, Args, [&]() {
|
|
|
|
return getOrCreateVReg(*CI.getCalledValue());
|
|
|
|
});
|
2016-08-11 05:44:01 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
Intrinsic::ID ID = F->getIntrinsicID();
|
2016-07-30 06:32:36 +08:00
|
|
|
if (TII && ID == Intrinsic::not_intrinsic)
|
2016-08-11 05:44:01 +08:00
|
|
|
ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
|
2016-07-30 06:32:36 +08:00
|
|
|
|
2016-08-11 05:44:01 +08:00
|
|
|
assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
|
2016-07-30 06:32:36 +08:00
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
if (translateKnownIntrinsic(CI, ID, MIRBuilder))
|
2016-08-20 01:17:06 +08:00
|
|
|
return true;
|
|
|
|
|
2016-07-30 06:32:36 +08:00
|
|
|
unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
|
|
|
|
MachineInstrBuilder MIB =
|
2016-09-09 19:46:34 +08:00
|
|
|
MIRBuilder.buildIntrinsic(ID, Res, !CI.doesNotAccessMemory());
|
2016-07-30 06:32:36 +08:00
|
|
|
|
|
|
|
for (auto &Arg : CI.arg_operands()) {
|
2017-03-08 04:53:09 +08:00
|
|
|
// Some intrinsics take metadata parameters. Reject them.
|
|
|
|
if (isa<MetadataAsValue>(Arg))
|
|
|
|
return false;
|
2016-07-30 06:32:36 +08:00
|
|
|
if (ConstantInt *CI = dyn_cast<ConstantInt>(Arg))
|
|
|
|
MIB.addImm(CI->getSExtValue());
|
|
|
|
else
|
|
|
|
MIB.addUse(getOrCreateVReg(*Arg));
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
bool IRTranslator::translateInvoke(const User &U,
|
|
|
|
MachineIRBuilder &MIRBuilder) {
|
2016-11-10 06:39:54 +08:00
|
|
|
const InvokeInst &I = cast<InvokeInst>(U);
|
2016-12-08 05:17:47 +08:00
|
|
|
MCContext &Context = MF->getContext();
|
2016-11-10 06:39:54 +08:00
|
|
|
|
|
|
|
const BasicBlock *ReturnBB = I.getSuccessor(0);
|
|
|
|
const BasicBlock *EHPadBB = I.getSuccessor(1);
|
|
|
|
|
|
|
|
const Value *Callee(I.getCalledValue());
|
|
|
|
const Function *Fn = dyn_cast<Function>(Callee);
|
|
|
|
if (isa<InlineAsm>(Callee))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// FIXME: support invoking patchpoint and statepoint intrinsics.
|
|
|
|
if (Fn && Fn->isIntrinsic())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// FIXME: support whatever these are.
|
|
|
|
if (I.countOperandBundlesOfType(LLVMContext::OB_deopt))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// FIXME: support Windows exception handling.
|
|
|
|
if (!isa<LandingPadInst>(EHPadBB->front()))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
2016-12-02 03:32:15 +08:00
|
|
|
// Emit the actual call, bracketed by EH_LABELs so that the MF knows about
|
2016-11-10 06:39:54 +08:00
|
|
|
// the region covered by the try.
|
2016-12-02 03:32:15 +08:00
|
|
|
MCSymbol *BeginSymbol = Context.createTempSymbol();
|
2016-11-10 06:39:54 +08:00
|
|
|
MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
|
|
|
|
|
|
|
|
unsigned Res = I.getType()->isVoidTy() ? 0 : getOrCreateVReg(I);
|
2017-02-01 02:36:11 +08:00
|
|
|
SmallVector<unsigned, 8> Args;
|
2016-11-10 06:39:54 +08:00
|
|
|
for (auto &Arg: I.arg_operands())
|
2017-02-01 02:36:11 +08:00
|
|
|
Args.push_back(getOrCreateVReg(*Arg));
|
2016-11-10 06:39:54 +08:00
|
|
|
|
2017-02-01 02:36:11 +08:00
|
|
|
CLI->lowerCall(MIRBuilder, I, Res, Args,
|
|
|
|
[&]() { return getOrCreateVReg(*I.getCalledValue()); });
|
2016-11-10 06:39:54 +08:00
|
|
|
|
2016-12-02 03:32:15 +08:00
|
|
|
MCSymbol *EndSymbol = Context.createTempSymbol();
|
2016-11-10 06:39:54 +08:00
|
|
|
MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
|
|
|
|
|
|
|
|
// FIXME: track probabilities.
|
|
|
|
MachineBasicBlock &EHPadMBB = getOrCreateBB(*EHPadBB),
|
|
|
|
&ReturnMBB = getOrCreateBB(*ReturnBB);
|
2016-12-08 05:17:47 +08:00
|
|
|
MF->addInvoke(&EHPadMBB, BeginSymbol, EndSymbol);
|
2016-11-10 06:39:54 +08:00
|
|
|
MIRBuilder.getMBB().addSuccessor(&ReturnMBB);
|
|
|
|
MIRBuilder.getMBB().addSuccessor(&EHPadMBB);
|
2017-02-01 04:12:18 +08:00
|
|
|
MIRBuilder.buildBr(ReturnMBB);
|
2016-11-10 06:39:54 +08:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
bool IRTranslator::translateLandingPad(const User &U,
|
|
|
|
MachineIRBuilder &MIRBuilder) {
|
2016-11-10 06:39:54 +08:00
|
|
|
const LandingPadInst &LP = cast<LandingPadInst>(U);
|
|
|
|
|
|
|
|
MachineBasicBlock &MBB = MIRBuilder.getMBB();
|
2016-12-02 03:32:15 +08:00
|
|
|
addLandingPadInfo(LP, MBB);
|
2016-11-10 06:39:54 +08:00
|
|
|
|
|
|
|
MBB.setIsEHPad();
|
|
|
|
|
|
|
|
// If there aren't registers to copy the values into (e.g., during SjLj
|
|
|
|
// exceptions), then don't bother.
|
2016-12-08 05:17:47 +08:00
|
|
|
auto &TLI = *MF->getSubtarget().getTargetLowering();
|
|
|
|
const Constant *PersonalityFn = MF->getFunction()->getPersonalityFn();
|
2016-11-10 06:39:54 +08:00
|
|
|
if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
|
|
|
|
TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// If landingpad's return type is token type, we don't create DAG nodes
|
|
|
|
// for its exception pointer and selector value. The extraction of exception
|
|
|
|
// pointer or selector value from token type landingpads is not currently
|
|
|
|
// supported.
|
|
|
|
if (LP.getType()->isTokenTy())
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Add a label to mark the beginning of the landing pad. Deletion of the
|
|
|
|
// landing pad can thus be detected via the MachineModuleInfo.
|
|
|
|
MIRBuilder.buildInstr(TargetOpcode::EH_LABEL)
|
2016-12-08 05:17:47 +08:00
|
|
|
.addSym(MF->addLandingPad(&MBB));
|
2016-11-10 06:39:54 +08:00
|
|
|
|
2017-03-08 07:04:06 +08:00
|
|
|
LLT Ty{*LP.getType(), *DL};
|
|
|
|
unsigned Undef = MRI->createGenericVirtualRegister(Ty);
|
|
|
|
MIRBuilder.buildUndef(Undef);
|
|
|
|
|
2017-01-25 08:16:53 +08:00
|
|
|
SmallVector<LLT, 2> Tys;
|
|
|
|
for (Type *Ty : cast<StructType>(LP.getType())->elements())
|
2017-03-08 03:21:23 +08:00
|
|
|
Tys.push_back(LLT{*Ty, *DL});
|
2017-01-25 08:16:53 +08:00
|
|
|
assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
|
|
|
|
|
2016-11-10 06:39:54 +08:00
|
|
|
// Mark exception register as live in.
|
2017-03-08 07:04:06 +08:00
|
|
|
unsigned ExceptionReg = TLI.getExceptionPointerRegister(PersonalityFn);
|
|
|
|
if (!ExceptionReg)
|
|
|
|
return false;
|
2016-11-10 06:39:54 +08:00
|
|
|
|
2017-03-08 07:04:06 +08:00
|
|
|
MBB.addLiveIn(ExceptionReg);
|
|
|
|
unsigned VReg = MRI->createGenericVirtualRegister(Tys[0]),
|
|
|
|
Tmp = MRI->createGenericVirtualRegister(Ty);
|
|
|
|
MIRBuilder.buildCopy(VReg, ExceptionReg);
|
|
|
|
MIRBuilder.buildInsert(Tmp, Undef, VReg, 0);
|
|
|
|
|
|
|
|
unsigned SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
|
|
|
|
if (!SelectorReg)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
MBB.addLiveIn(SelectorReg);
|
|
|
|
|
|
|
|
// N.b. the exception selector register always has pointer type and may not
|
|
|
|
// match the actual IR-level type in the landingpad so an extra cast is
|
|
|
|
// needed.
|
|
|
|
unsigned PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
|
|
|
|
MIRBuilder.buildCopy(PtrVReg, SelectorReg);
|
2016-11-10 06:39:54 +08:00
|
|
|
|
2017-03-08 07:04:06 +08:00
|
|
|
VReg = MRI->createGenericVirtualRegister(Tys[1]);
|
|
|
|
MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT).addDef(VReg).addUse(PtrVReg);
|
|
|
|
MIRBuilder.buildInsert(getOrCreateVReg(LP), Tmp, VReg,
|
|
|
|
Tys[0].getSizeInBits());
|
2016-11-10 06:39:54 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-02-04 02:22:45 +08:00
|
|
|
bool IRTranslator::translateAlloca(const User &U,
|
|
|
|
MachineIRBuilder &MIRBuilder) {
|
|
|
|
auto &AI = cast<AllocaInst>(U);
|
|
|
|
|
|
|
|
if (AI.isStaticAlloca()) {
|
|
|
|
unsigned Res = getOrCreateVReg(AI);
|
|
|
|
int FI = getOrCreateFrameIndex(AI);
|
|
|
|
MIRBuilder.buildFrameIndex(Res, FI);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Now we're in the harder dynamic case.
|
|
|
|
Type *Ty = AI.getAllocatedType();
|
|
|
|
unsigned Align =
|
|
|
|
std::max((unsigned)DL->getPrefTypeAlignment(Ty), AI.getAlignment());
|
|
|
|
|
|
|
|
unsigned NumElts = getOrCreateVReg(*AI.getArraySize());
|
|
|
|
|
|
|
|
LLT IntPtrTy = LLT::scalar(DL->getPointerSizeInBits());
|
|
|
|
if (MRI->getType(NumElts) != IntPtrTy) {
|
|
|
|
unsigned ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
|
|
|
|
MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
|
|
|
|
NumElts = ExtElts;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned AllocSize = MRI->createGenericVirtualRegister(IntPtrTy);
|
|
|
|
unsigned TySize = MRI->createGenericVirtualRegister(IntPtrTy);
|
2017-02-15 04:56:18 +08:00
|
|
|
MIRBuilder.buildConstant(TySize, -DL->getTypeAllocSize(Ty));
|
2017-02-04 02:22:45 +08:00
|
|
|
MIRBuilder.buildMul(AllocSize, NumElts, TySize);
|
|
|
|
|
2017-03-08 03:21:23 +08:00
|
|
|
LLT PtrTy = LLT{*AI.getType(), *DL};
|
2017-02-04 02:22:45 +08:00
|
|
|
auto &TLI = *MF->getSubtarget().getTargetLowering();
|
|
|
|
unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
|
|
|
|
|
|
|
|
unsigned SPTmp = MRI->createGenericVirtualRegister(PtrTy);
|
|
|
|
MIRBuilder.buildCopy(SPTmp, SPReg);
|
|
|
|
|
2017-02-15 04:56:18 +08:00
|
|
|
unsigned AllocTmp = MRI->createGenericVirtualRegister(PtrTy);
|
|
|
|
MIRBuilder.buildGEP(AllocTmp, SPTmp, AllocSize);
|
2017-02-04 02:22:45 +08:00
|
|
|
|
|
|
|
// Handle alignment. We have to realign if the allocation granule was smaller
|
|
|
|
// than stack alignment, or the specific alloca requires more than stack
|
|
|
|
// alignment.
|
|
|
|
unsigned StackAlign =
|
|
|
|
MF->getSubtarget().getFrameLowering()->getStackAlignment();
|
|
|
|
Align = std::max(Align, StackAlign);
|
|
|
|
if (Align > StackAlign || DL->getTypeAllocSize(Ty) % StackAlign != 0) {
|
|
|
|
// Round the size of the allocation up to the stack alignment size
|
|
|
|
// by add SA-1 to the size. This doesn't overflow because we're computing
|
|
|
|
// an address inside an alloca.
|
2017-02-15 04:56:18 +08:00
|
|
|
unsigned AlignedAlloc = MRI->createGenericVirtualRegister(PtrTy);
|
|
|
|
MIRBuilder.buildPtrMask(AlignedAlloc, AllocTmp, Log2_32(Align));
|
|
|
|
AllocTmp = AlignedAlloc;
|
2017-02-04 02:22:45 +08:00
|
|
|
}
|
|
|
|
|
2017-02-15 04:56:18 +08:00
|
|
|
MIRBuilder.buildCopy(SPReg, AllocTmp);
|
|
|
|
MIRBuilder.buildCopy(getOrCreateVReg(AI), AllocTmp);
|
2016-08-27 07:49:05 +08:00
|
|
|
|
2017-02-04 02:22:45 +08:00
|
|
|
MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, &AI);
|
|
|
|
assert(MF->getFrameInfo().hasVarSizedObjects());
|
2016-07-23 00:59:52 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-02-16 07:22:33 +08:00
|
|
|
bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
|
|
|
|
// FIXME: We may need more info about the type. Because of how LLT works,
|
|
|
|
// we're completely discarding the i64/double distinction here (amongst
|
|
|
|
// others). Fortunately the ABIs I know of where that matters don't use va_arg
|
|
|
|
// anyway but that's not guaranteed.
|
|
|
|
MIRBuilder.buildInstr(TargetOpcode::G_VAARG)
|
|
|
|
.addDef(getOrCreateVReg(U))
|
|
|
|
.addUse(getOrCreateVReg(*U.getOperand(0)))
|
|
|
|
.addImm(DL->getABITypeAlignment(U.getType()));
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-12-08 05:29:15 +08:00
|
|
|
bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
|
2016-08-11 07:02:41 +08:00
|
|
|
const PHINode &PI = cast<PHINode>(U);
|
2016-09-09 19:47:31 +08:00
|
|
|
auto MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
|
2016-08-06 01:16:40 +08:00
|
|
|
MIB.addDef(getOrCreateVReg(PI));
|
|
|
|
|
|
|
|
PendingPHIs.emplace_back(&PI, MIB.getInstr());
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void IRTranslator::finishPendingPhis() {
|
|
|
|
for (std::pair<const PHINode *, MachineInstr *> &Phi : PendingPHIs) {
|
|
|
|
const PHINode *PI = Phi.first;
|
2016-12-08 05:29:15 +08:00
|
|
|
MachineInstrBuilder MIB(*MF, Phi.second);
|
2016-08-06 01:16:40 +08:00
|
|
|
|
|
|
|
// All MachineBasicBlocks exist, add them to the PHI. We assume IRTranslator
|
|
|
|
// won't create extra control flow here, otherwise we need to find the
|
|
|
|
// dominating predecessor here (or perhaps force the weirder IRTranslators
|
|
|
|
// to provide a simple boundary).
|
2017-01-18 06:13:50 +08:00
|
|
|
SmallSet<const BasicBlock *, 4> HandledPreds;
|
|
|
|
|
2016-08-06 01:16:40 +08:00
|
|
|
for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
|
2017-01-18 06:13:50 +08:00
|
|
|
auto IRPred = PI->getIncomingBlock(i);
|
|
|
|
if (HandledPreds.count(IRPred))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
HandledPreds.insert(IRPred);
|
|
|
|
unsigned ValReg = getOrCreateVReg(*PI->getIncomingValue(i));
|
|
|
|
for (auto Pred : getMachinePredBBs({IRPred, PI->getParent()})) {
|
|
|
|
assert(Pred->isSuccessor(MIB->getParent()) &&
|
|
|
|
"incorrect CFG at MachineBasicBlock level");
|
|
|
|
MIB.addUse(ValReg);
|
|
|
|
MIB.addMBB(Pred);
|
|
|
|
}
|
2016-08-06 01:16:40 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-02-11 06:59:27 +08:00
|
|
|
bool IRTranslator::translate(const Instruction &Inst) {
|
2016-12-08 05:29:15 +08:00
|
|
|
CurBuilder.setDebugLoc(Inst.getDebugLoc());
|
2016-02-11 06:59:27 +08:00
|
|
|
switch(Inst.getOpcode()) {
|
2016-08-11 07:02:41 +08:00
|
|
|
#define HANDLE_INST(NUM, OPCODE, CLASS) \
|
2016-12-08 05:29:15 +08:00
|
|
|
case Instruction::OPCODE: return translate##OPCODE(Inst, CurBuilder);
|
2016-08-11 07:02:41 +08:00
|
|
|
#include "llvm/IR/Instruction.def"
|
2016-02-12 02:53:28 +08:00
|
|
|
default:
|
2016-08-27 07:49:05 +08:00
|
|
|
if (!TPC->isGlobalISelAbortEnabled())
|
|
|
|
return false;
|
2016-08-11 07:02:41 +08:00
|
|
|
llvm_unreachable("unknown opcode");
|
2016-02-11 06:59:27 +08:00
|
|
|
}
|
2016-01-21 04:58:56 +08:00
|
|
|
}
|
|
|
|
|
2016-08-10 05:28:04 +08:00
|
|
|
bool IRTranslator::translate(const Constant &C, unsigned Reg) {
|
2016-08-10 07:01:30 +08:00
|
|
|
if (auto CI = dyn_cast<ConstantInt>(&C))
|
2016-12-06 05:54:17 +08:00
|
|
|
EntryBuilder.buildConstant(Reg, *CI);
|
2016-08-20 04:09:15 +08:00
|
|
|
else if (auto CF = dyn_cast<ConstantFP>(&C))
|
2016-09-09 19:46:34 +08:00
|
|
|
EntryBuilder.buildFConstant(Reg, *CF);
|
2016-08-10 07:01:30 +08:00
|
|
|
else if (isa<UndefValue>(C))
|
2017-03-07 02:36:40 +08:00
|
|
|
EntryBuilder.buildUndef(Reg);
|
2016-08-12 05:40:55 +08:00
|
|
|
else if (isa<ConstantPointerNull>(C))
|
2016-12-06 05:47:07 +08:00
|
|
|
EntryBuilder.buildConstant(Reg, 0);
|
2016-09-12 20:10:41 +08:00
|
|
|
else if (auto GV = dyn_cast<GlobalValue>(&C))
|
|
|
|
EntryBuilder.buildGlobalValue(Reg, GV);
|
2016-08-11 07:02:41 +08:00
|
|
|
else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
|
|
|
|
switch(CE->getOpcode()) {
|
|
|
|
#define HANDLE_INST(NUM, OPCODE, CLASS) \
|
2016-12-08 05:29:15 +08:00
|
|
|
case Instruction::OPCODE: return translate##OPCODE(*CE, EntryBuilder);
|
2016-08-11 07:02:41 +08:00
|
|
|
#include "llvm/IR/Instruction.def"
|
|
|
|
default:
|
2016-08-27 07:49:05 +08:00
|
|
|
if (!TPC->isGlobalISelAbortEnabled())
|
|
|
|
return false;
|
2016-08-11 07:02:41 +08:00
|
|
|
llvm_unreachable("unknown opcode");
|
|
|
|
}
|
2016-08-27 07:49:05 +08:00
|
|
|
} else if (!TPC->isGlobalISelAbortEnabled())
|
|
|
|
return false;
|
|
|
|
else
|
2016-08-10 07:01:30 +08:00
|
|
|
llvm_unreachable("unhandled constant kind");
|
2016-08-10 05:28:04 +08:00
|
|
|
|
2016-08-10 07:01:30 +08:00
|
|
|
return true;
|
2016-08-10 05:28:04 +08:00
|
|
|
}
|
|
|
|
|
2016-08-12 00:21:29 +08:00
|
|
|
void IRTranslator::finalizeFunction() {
|
2016-02-11 06:59:27 +08:00
|
|
|
// Release the memory used by the different maps we
|
|
|
|
// needed during the translation.
|
2016-12-06 07:10:19 +08:00
|
|
|
PendingPHIs.clear();
|
2016-02-12 05:48:32 +08:00
|
|
|
ValToVReg.clear();
|
2016-11-01 02:30:59 +08:00
|
|
|
FrameIndices.clear();
|
2016-02-11 06:59:27 +08:00
|
|
|
Constants.clear();
|
2017-01-18 06:13:50 +08:00
|
|
|
MachinePreds.clear();
|
2016-01-21 04:58:56 +08:00
|
|
|
}
|
|
|
|
|
2016-12-08 05:17:47 +08:00
|
|
|
bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
|
|
|
|
MF = &CurMF;
|
|
|
|
const Function &F = *MF->getFunction();
|
2016-02-12 03:59:41 +08:00
|
|
|
if (F.empty())
|
|
|
|
return false;
|
2016-12-08 05:17:47 +08:00
|
|
|
CLI = MF->getSubtarget().getCallLowering();
|
2016-12-08 05:29:15 +08:00
|
|
|
CurBuilder.setMF(*MF);
|
2016-12-08 05:17:47 +08:00
|
|
|
EntryBuilder.setMF(*MF);
|
|
|
|
MRI = &MF->getRegInfo();
|
2016-07-23 00:59:52 +08:00
|
|
|
DL = &F.getParent()->getDataLayout();
|
2016-08-27 07:49:05 +08:00
|
|
|
TPC = &getAnalysis<TargetPassConfig>();
|
2017-02-24 05:05:42 +08:00
|
|
|
ORE = make_unique<OptimizationRemarkEmitter>(&F);
|
2016-07-23 00:59:52 +08:00
|
|
|
|
2016-08-06 01:50:36 +08:00
|
|
|
assert(PendingPHIs.empty() && "stale PHIs");
|
|
|
|
|
2017-02-24 07:57:28 +08:00
|
|
|
// Release the per-function state when we return, whether we succeeded or not.
|
|
|
|
auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
|
|
|
|
|
2016-12-08 05:05:38 +08:00
|
|
|
// Setup a separate basic-block for the arguments and constants, falling
|
|
|
|
// through to the IR-level Function's entry block.
|
2016-12-08 05:17:47 +08:00
|
|
|
MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
|
|
|
|
MF->push_back(EntryBB);
|
2016-12-08 05:05:38 +08:00
|
|
|
EntryBB->addSuccessor(&getOrCreateBB(F.front()));
|
|
|
|
EntryBuilder.setMBB(*EntryBB);
|
|
|
|
|
|
|
|
// Lower the actual args into this basic block.
|
2016-02-12 03:59:41 +08:00
|
|
|
SmallVector<unsigned, 8> VRegArgs;
|
|
|
|
for (const Argument &Arg: F.args())
|
2016-03-12 01:27:54 +08:00
|
|
|
VRegArgs.push_back(getOrCreateVReg(Arg));
|
2017-02-24 08:34:41 +08:00
|
|
|
if (!CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs)) {
|
2017-02-24 08:34:44 +08:00
|
|
|
OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
|
|
|
|
MF->getFunction()->getSubprogram(),
|
2017-02-24 05:05:42 +08:00
|
|
|
&MF->getFunction()->getEntryBlock());
|
|
|
|
R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
|
|
|
|
reportTranslationError(*MF, *TPC, *ORE, R);
|
|
|
|
return false;
|
2016-08-27 07:49:05 +08:00
|
|
|
}
|
2016-02-12 03:59:41 +08:00
|
|
|
|
2016-12-08 05:05:38 +08:00
|
|
|
// And translate the function!
|
2016-02-11 06:59:27 +08:00
|
|
|
for (const BasicBlock &BB: F) {
|
2016-03-12 01:27:43 +08:00
|
|
|
MachineBasicBlock &MBB = getOrCreateBB(BB);
|
2016-03-12 01:27:47 +08:00
|
|
|
// Set the insertion point of all the following translations to
|
|
|
|
// the end of this basic block.
|
2016-12-08 05:29:15 +08:00
|
|
|
CurBuilder.setMBB(MBB);
|
2016-11-10 06:39:54 +08:00
|
|
|
|
2016-02-11 06:59:27 +08:00
|
|
|
for (const Instruction &Inst: BB) {
|
2017-02-24 08:34:41 +08:00
|
|
|
if (translate(Inst))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
std::string InstStrStorage;
|
|
|
|
raw_string_ostream InstStr(InstStrStorage);
|
|
|
|
InstStr << Inst;
|
|
|
|
|
2017-02-24 08:34:47 +08:00
|
|
|
OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
|
|
|
|
Inst.getDebugLoc(), &BB);
|
2017-02-24 08:34:41 +08:00
|
|
|
R << "unable to translate instruction: " << ore::NV("Opcode", &Inst)
|
|
|
|
<< ": '" << InstStr.str() << "'";
|
|
|
|
reportTranslationError(*MF, *TPC, *ORE, R);
|
|
|
|
return false;
|
2016-02-11 06:59:27 +08:00
|
|
|
}
|
|
|
|
}
|
2016-07-13 06:23:42 +08:00
|
|
|
|
2017-02-24 07:57:36 +08:00
|
|
|
finishPendingPhis();
|
|
|
|
|
|
|
|
// Now that the MachineFrameInfo has been configured, no further changes to
|
|
|
|
// the reserved registers are possible.
|
|
|
|
MRI->freezeReservedRegs(*MF);
|
|
|
|
|
|
|
|
// Merge the argument lowering and constants block with its single
|
|
|
|
// successor, the LLVM-IR entry block. We want the basic block to
|
|
|
|
// be maximal.
|
|
|
|
assert(EntryBB->succ_size() == 1 &&
|
|
|
|
"Custom BB used for lowering should have only one successor");
|
|
|
|
// Get the successor of the current entry block.
|
|
|
|
MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
|
|
|
|
assert(NewEntryBB.pred_size() == 1 &&
|
|
|
|
"LLVM-IR entry block has a predecessor!?");
|
|
|
|
// Move all the instruction from the current entry block to the
|
|
|
|
// new entry block.
|
|
|
|
NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
|
|
|
|
EntryBB->end());
|
|
|
|
|
|
|
|
// Update the live-in information for the new entry block.
|
|
|
|
for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
|
|
|
|
NewEntryBB.addLiveIn(LiveIn);
|
|
|
|
NewEntryBB.sortUniqueLiveIns();
|
|
|
|
|
|
|
|
// Get rid of the now empty basic block.
|
|
|
|
EntryBB->removeSuccessor(&NewEntryBB);
|
|
|
|
MF->remove(EntryBB);
|
|
|
|
MF->DeleteMachineBasicBlock(EntryBB);
|
|
|
|
|
|
|
|
assert(&MF->front() == &NewEntryBB &&
|
|
|
|
"New entry wasn't next in the list of basic block!");
|
2016-08-06 01:16:40 +08:00
|
|
|
|
2016-01-21 04:58:56 +08:00
|
|
|
return false;
|
|
|
|
}
|