2017-06-07 06:22:41 +08:00
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//===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------------===//
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2009-06-27 05:28:53 +08:00
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2009-06-27 05:28:53 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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2009-07-03 06:18:33 +08:00
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// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
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2009-06-27 05:28:53 +08:00
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//
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//===----------------------------------------------------------------------===//
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2017-11-17 09:07:10 +08:00
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#include "Thumb2InstrInfo.h"
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2009-06-27 05:28:53 +08:00
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#include "ARMMachineFunctionInfo.h"
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2011-07-21 07:34:39 +08:00
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#include "MCTargetDesc/ARMAddressingModes.h"
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2017-06-07 06:22:41 +08:00
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#include "llvm/CodeGen/MachineBasicBlock.h"
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2009-06-27 05:28:53 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2017-06-07 06:22:41 +08:00
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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2009-06-27 05:28:53 +08:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2009-11-02 06:04:35 +08:00
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#include "llvm/CodeGen/MachineMemOperand.h"
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2017-06-07 06:22:41 +08:00
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#include "llvm/CodeGen/MachineOperand.h"
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2013-04-21 19:57:07 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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2017-06-07 06:22:41 +08:00
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#include "llvm/IR/DebugLoc.h"
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2012-02-29 07:53:30 +08:00
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#include "llvm/MC/MCInst.h"
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2017-06-07 06:22:41 +08:00
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#include "llvm/MC/MCInstrDesc.h"
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2010-06-26 06:42:03 +08:00
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#include "llvm/Support/CommandLine.h"
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2017-06-07 06:22:41 +08:00
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cassert>
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2009-06-27 05:28:53 +08:00
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using namespace llvm;
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2010-10-02 04:28:06 +08:00
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static cl::opt<bool>
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OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
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cl::desc("Use old-style Thumb2 if-conversion heuristics"),
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cl::init(false));
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2009-11-02 08:10:38 +08:00
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Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
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2017-06-07 06:22:41 +08:00
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: ARMBaseInstrInfo(STI) {}
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2009-06-27 05:28:53 +08:00
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2017-04-22 05:48:41 +08:00
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/// Return the noop instruction to use for a noop.
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void Thumb2InstrInfo::getNoop(MCInst &NopInst) const {
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2013-10-18 22:09:49 +08:00
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NopInst.setOpcode(ARM::tHINT);
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2015-05-14 02:37:00 +08:00
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NopInst.addOperand(MCOperand::createImm(0));
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NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
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NopInst.addOperand(MCOperand::createReg(0));
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2012-02-29 07:53:30 +08:00
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}
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2009-07-11 14:43:01 +08:00
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unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
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2009-07-09 00:09:28 +08:00
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// FIXME
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return 0;
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}
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2010-06-19 07:09:54 +08:00
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void
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Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
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MachineBasicBlock *NewDest) const {
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MachineBasicBlock *MBB = Tail->getParent();
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ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
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2016-06-09 19:51:29 +08:00
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if (!AFI->hasITBlocks() || Tail->isBranch()) {
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2012-11-28 10:35:17 +08:00
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TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
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2010-06-19 07:09:54 +08:00
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return;
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}
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// If the first instruction of Tail is predicated, we may have to update
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// the IT instruction.
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unsigned PredReg = 0;
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2016-02-23 10:46:52 +08:00
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ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
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2010-06-19 07:09:54 +08:00
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MachineBasicBlock::iterator MBBI = Tail;
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if (CC != ARMCC::AL)
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// Expecting at least the t2IT instruction before it.
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--MBBI;
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// Actually replace the tail.
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2012-11-28 10:35:17 +08:00
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TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
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2010-06-19 07:09:54 +08:00
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// Fix up IT.
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if (CC != ARMCC::AL) {
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MachineBasicBlock::iterator E = MBB->begin();
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unsigned Count = 4; // At most 4 instructions in an IT block.
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while (Count && MBBI != E) {
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2018-05-09 10:42:00 +08:00
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if (MBBI->isDebugInstr()) {
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2010-06-19 07:09:54 +08:00
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--MBBI;
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continue;
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}
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if (MBBI->getOpcode() == ARM::t2IT) {
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unsigned Mask = MBBI->getOperand(1).getImm();
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if (Count == 4)
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MBBI->eraseFromParent();
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else {
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unsigned MaskOn = 1 << Count;
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unsigned MaskOff = ~(MaskOn - 1);
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MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
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}
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return;
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}
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--MBBI;
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--Count;
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}
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// Ctrl flow can reach here if branch folding is run before IT block
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// formation pass.
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}
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}
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2010-06-22 09:18:16 +08:00
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bool
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Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) const {
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2018-05-09 10:42:00 +08:00
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while (MBBI->isDebugInstr()) {
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2011-02-22 07:40:47 +08:00
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++MBBI;
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2011-02-22 15:07:59 +08:00
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if (MBBI == MBB.end())
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return false;
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}
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2011-02-22 07:40:47 +08:00
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2010-06-22 09:18:16 +08:00
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unsigned PredReg = 0;
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2016-02-23 10:46:52 +08:00
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return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;
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2010-06-26 06:42:03 +08:00
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}
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2010-06-22 09:18:16 +08:00
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2010-07-11 14:33:54 +08:00
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void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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2016-06-12 23:39:02 +08:00
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MachineBasicBlock::iterator I,
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const DebugLoc &DL, unsigned DestReg,
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unsigned SrcReg, bool KillSrc) const {
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2009-07-27 08:33:08 +08:00
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// Handle SPR, DPR, and QPR copies.
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2010-07-11 14:33:54 +08:00
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if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
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return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
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2017-01-13 17:37:56 +08:00
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BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.add(predOps(ARMCC::AL));
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2009-07-17 07:26:06 +08:00
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}
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2009-07-27 11:14:20 +08:00
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void Thumb2InstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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2010-05-07 03:06:44 +08:00
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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2013-04-21 19:57:07 +08:00
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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2016-07-29 02:40:00 +08:00
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MachineFrameInfo &MFI = MF.getFrameInfo();
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2015-08-12 07:09:45 +08:00
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
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MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
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2013-04-21 19:57:07 +08:00
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2018-11-08 21:02:10 +08:00
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if (ARM::GPRRegClass.hasSubClassEq(RC)) {
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2017-01-13 17:37:56 +08:00
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BuildMI(MBB, I, DL, get(ARM::t2STRi12))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO)
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.add(predOps(ARMCC::AL));
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2009-07-27 11:14:20 +08:00
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return;
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}
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2013-04-21 19:57:07 +08:00
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if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
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// Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
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// gsub_0, but needs an extra constraint for gsub_1 (which could be sp
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// otherwise).
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2016-06-01 05:39:12 +08:00
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if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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[ARM] Add the non-MVE instructions in Arm v8.1-M.
This adds support for the new family of conditional selection /
increment / negation instructions; the low-overhead branch
instructions (e.g. BF, WLS, DLS); the CLRM instruction to zero a whole
list of registers at once; the new VMRS/VMSR and VLDR/VSTR
instructions to get data in and out of 8.1-M system registers,
particularly including the new VPR register used by MVE vector
predication.
To support this, we also add a register name 'zr' (used by the CSEL
family to force one of the inputs to the constant 0), and operand
types for lists of registers that are also allowed to include APSR or
VPR (used by CLRM). The VLDR/VSTR instructions also need a new
addressing mode.
The low-overhead branch instructions exist in their own separate
architecture extension, which we treat as enabled by default, but you
can say -mattr=-lob or equivalent to turn it off.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Reviewed By: samparker
Subscribers: miyuki, javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62667
llvm-svn: 363039
2019-06-11 17:29:18 +08:00
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MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_GPRwithAPSRnospRegClass);
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2016-06-01 05:39:12 +08:00
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}
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2013-04-21 19:57:07 +08:00
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
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AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
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AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
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2017-01-13 17:37:56 +08:00
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MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
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2013-04-21 19:57:07 +08:00
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return;
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}
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2010-05-07 03:06:44 +08:00
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ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
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2009-07-27 11:14:20 +08:00
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}
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void Thumb2InstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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2010-05-07 03:06:44 +08:00
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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2013-04-21 19:57:07 +08:00
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MachineFunction &MF = *MBB.getParent();
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2016-07-29 02:40:00 +08:00
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MachineFrameInfo &MFI = MF.getFrameInfo();
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2015-08-12 07:09:45 +08:00
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
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2013-04-21 19:57:07 +08:00
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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2018-11-08 21:02:10 +08:00
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if (ARM::GPRRegClass.hasSubClassEq(RC)) {
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2017-01-13 17:37:56 +08:00
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BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO)
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.add(predOps(ARMCC::AL));
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2009-07-27 11:14:20 +08:00
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return;
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}
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2013-04-21 19:57:07 +08:00
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if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
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// Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
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// gsub_0, but needs an extra constraint for gsub_1 (which could be sp
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// otherwise).
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2016-06-01 05:39:12 +08:00
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if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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MRI->constrainRegClass(DestReg,
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[ARM] Add the non-MVE instructions in Arm v8.1-M.
This adds support for the new family of conditional selection /
increment / negation instructions; the low-overhead branch
instructions (e.g. BF, WLS, DLS); the CLRM instruction to zero a whole
list of registers at once; the new VMRS/VMSR and VLDR/VSTR
instructions to get data in and out of 8.1-M system registers,
particularly including the new VPR register used by MVE vector
predication.
To support this, we also add a register name 'zr' (used by the CSEL
family to force one of the inputs to the constant 0), and operand
types for lists of registers that are also allowed to include APSR or
VPR (used by CLRM). The VLDR/VSTR instructions also need a new
addressing mode.
The low-overhead branch instructions exist in their own separate
architecture extension, which we treat as enabled by default, but you
can say -mattr=-lob or equivalent to turn it off.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Reviewed By: samparker
Subscribers: miyuki, javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62667
llvm-svn: 363039
2019-06-11 17:29:18 +08:00
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&ARM::GPRPair_with_gsub_1_in_GPRwithAPSRnospRegClass);
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2016-06-01 05:39:12 +08:00
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}
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2013-04-21 19:57:07 +08:00
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
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AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
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AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
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2017-01-13 17:37:56 +08:00
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MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
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2013-04-21 19:57:07 +08:00
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if (TargetRegisterInfo::isPhysicalRegister(DestReg))
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MIB.addReg(DestReg, RegState::ImplicitDefine);
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return;
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}
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2010-05-07 03:06:44 +08:00
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ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
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2009-07-27 11:14:20 +08:00
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}
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2009-07-28 13:48:47 +08:00
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2016-06-28 23:18:26 +08:00
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void Thumb2InstrInfo::expandLoadStackGuard(
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MachineBasicBlock::iterator MI) const {
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MachineFunction &MF = *MI->getParent()->getParent();
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if (MF.getTarget().isPositionIndependent())
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expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12);
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2014-08-02 13:40:40 +08:00
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else
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2016-06-28 23:18:26 +08:00
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expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12);
|
2014-07-26 03:31:34 +08:00
|
|
|
}
|
|
|
|
|
|
2009-07-28 13:48:47 +08:00
|
|
|
void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
|
2016-06-12 23:39:02 +08:00
|
|
|
MachineBasicBlock::iterator &MBBI,
|
|
|
|
|
const DebugLoc &dl, unsigned DestReg,
|
|
|
|
|
unsigned BaseReg, int NumBytes,
|
|
|
|
|
ARMCC::CondCodes Pred, unsigned PredReg,
|
|
|
|
|
const ARMBaseInstrInfo &TII,
|
|
|
|
|
unsigned MIFlags) {
|
2013-11-05 07:04:15 +08:00
|
|
|
if (NumBytes == 0 && DestReg != BaseReg) {
|
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
|
|
|
|
|
.addReg(BaseReg, RegState::Kill)
|
|
|
|
|
.addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2009-07-28 13:48:47 +08:00
|
|
|
bool isSub = NumBytes < 0;
|
|
|
|
|
if (isSub) NumBytes = -NumBytes;
|
|
|
|
|
|
|
|
|
|
// If profitable, use a movw or movt to materialize the offset.
|
|
|
|
|
// FIXME: Use the scavenger to grab a scratch register.
|
|
|
|
|
if (DestReg != ARM::SP && DestReg != BaseReg &&
|
|
|
|
|
NumBytes >= 4096 &&
|
|
|
|
|
ARM_AM::getT2SOImmVal(NumBytes) == -1) {
|
|
|
|
|
bool Fits = false;
|
|
|
|
|
if (NumBytes < 65536) {
|
|
|
|
|
// Use a movw to materialize the 16-bit constant.
|
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
|
|
|
|
|
.addImm(NumBytes)
|
2011-03-06 02:43:32 +08:00
|
|
|
.addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
|
2009-07-28 13:48:47 +08:00
|
|
|
Fits = true;
|
|
|
|
|
} else if ((NumBytes & 0xffff) == 0) {
|
|
|
|
|
// Use a movt to materialize the 32-bit constant.
|
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
|
|
|
|
|
.addReg(DestReg)
|
|
|
|
|
.addImm(NumBytes >> 16)
|
2011-03-06 02:43:32 +08:00
|
|
|
.addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
|
2009-07-28 13:48:47 +08:00
|
|
|
Fits = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (Fits) {
|
|
|
|
|
if (isSub) {
|
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
|
2017-01-20 16:15:24 +08:00
|
|
|
.addReg(BaseReg)
|
|
|
|
|
.addReg(DestReg, RegState::Kill)
|
|
|
|
|
.add(predOps(Pred, PredReg))
|
|
|
|
|
.add(condCodeOp())
|
|
|
|
|
.setMIFlags(MIFlags);
|
2009-07-28 13:48:47 +08:00
|
|
|
} else {
|
2015-05-01 02:52:49 +08:00
|
|
|
// Here we know that DestReg is not SP but we do not
|
|
|
|
|
// know anything about BaseReg. t2ADDrr is an invalid
|
|
|
|
|
// instruction is SP is used as the second argument, but
|
|
|
|
|
// is fine if SP is the first argument. To be sure we
|
|
|
|
|
// do not generate invalid encoding, put BaseReg first.
|
2009-07-28 13:48:47 +08:00
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
|
2017-01-20 16:15:24 +08:00
|
|
|
.addReg(BaseReg)
|
|
|
|
|
.addReg(DestReg, RegState::Kill)
|
|
|
|
|
.add(predOps(Pred, PredReg))
|
|
|
|
|
.add(condCodeOp())
|
|
|
|
|
.setMIFlags(MIFlags);
|
2009-07-28 13:48:47 +08:00
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
while (NumBytes) {
|
|
|
|
|
unsigned ThisVal = NumBytes;
|
2009-08-07 08:34:42 +08:00
|
|
|
unsigned Opc = 0;
|
|
|
|
|
if (DestReg == ARM::SP && BaseReg != ARM::SP) {
|
|
|
|
|
// mov sp, rn. Note t2MOVr cannot be used.
|
2017-01-13 17:37:56 +08:00
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
|
|
|
|
|
.addReg(BaseReg)
|
|
|
|
|
.setMIFlags(MIFlags)
|
|
|
|
|
.add(predOps(ARMCC::AL));
|
2009-08-07 08:34:42 +08:00
|
|
|
BaseReg = ARM::SP;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-09 06:56:15 +08:00
|
|
|
bool HasCCOut = true;
|
2009-08-07 08:34:42 +08:00
|
|
|
if (BaseReg == ARM::SP) {
|
|
|
|
|
// sub sp, sp, #imm7
|
|
|
|
|
if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
|
|
|
|
|
assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
|
|
|
|
|
Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
|
2017-01-13 17:37:56 +08:00
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
|
|
|
|
|
.addReg(BaseReg)
|
|
|
|
|
.addImm(ThisVal / 4)
|
|
|
|
|
.setMIFlags(MIFlags)
|
|
|
|
|
.add(predOps(ARMCC::AL));
|
2009-08-07 08:34:42 +08:00
|
|
|
NumBytes = 0;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// sub rd, sp, so_imm
|
2011-06-30 07:25:04 +08:00
|
|
|
Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
|
2009-08-07 08:34:42 +08:00
|
|
|
if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
|
|
|
|
|
NumBytes = 0;
|
|
|
|
|
} else {
|
|
|
|
|
// FIXME: Move this to ARMAddressingModes.h?
|
2013-05-25 06:23:49 +08:00
|
|
|
unsigned RotAmt = countLeadingZeros(ThisVal);
|
2009-08-07 08:34:42 +08:00
|
|
|
ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
|
|
|
|
|
NumBytes &= ~ThisVal;
|
|
|
|
|
assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
|
|
|
|
|
"Bit extraction didn't work?");
|
|
|
|
|
}
|
2009-07-28 13:48:47 +08:00
|
|
|
} else {
|
2009-08-07 08:34:42 +08:00
|
|
|
assert(DestReg != ARM::SP && BaseReg != ARM::SP);
|
|
|
|
|
Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
|
|
|
|
|
if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
|
|
|
|
|
NumBytes = 0;
|
|
|
|
|
} else if (ThisVal < 4096) {
|
|
|
|
|
Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
|
2010-03-09 06:56:15 +08:00
|
|
|
HasCCOut = false;
|
2009-08-07 08:34:42 +08:00
|
|
|
NumBytes = 0;
|
|
|
|
|
} else {
|
|
|
|
|
// FIXME: Move this to ARMAddressingModes.h?
|
2013-05-25 06:23:49 +08:00
|
|
|
unsigned RotAmt = countLeadingZeros(ThisVal);
|
2009-08-07 08:34:42 +08:00
|
|
|
ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
|
|
|
|
|
NumBytes &= ~ThisVal;
|
|
|
|
|
assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
|
|
|
|
|
"Bit extraction didn't work?");
|
|
|
|
|
}
|
2009-07-28 13:48:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Build the new ADD / SUB.
|
2017-01-13 17:37:56 +08:00
|
|
|
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
|
|
|
|
|
.addReg(BaseReg, RegState::Kill)
|
|
|
|
|
.addImm(ThisVal)
|
|
|
|
|
.add(predOps(ARMCC::AL))
|
|
|
|
|
.setMIFlags(MIFlags);
|
2010-03-09 06:56:15 +08:00
|
|
|
if (HasCCOut)
|
2017-01-13 18:18:01 +08:00
|
|
|
MIB.add(condCodeOp());
|
2009-08-07 08:34:42 +08:00
|
|
|
|
2009-07-28 13:48:47 +08:00
|
|
|
BaseReg = DestReg;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static unsigned
|
|
|
|
|
negativeOffsetOpcode(unsigned opcode)
|
|
|
|
|
{
|
|
|
|
|
switch (opcode) {
|
|
|
|
|
case ARM::t2LDRi12: return ARM::t2LDRi8;
|
|
|
|
|
case ARM::t2LDRHi12: return ARM::t2LDRHi8;
|
|
|
|
|
case ARM::t2LDRBi12: return ARM::t2LDRBi8;
|
|
|
|
|
case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
|
|
|
|
|
case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
|
|
|
|
|
case ARM::t2STRi12: return ARM::t2STRi8;
|
|
|
|
|
case ARM::t2STRBi12: return ARM::t2STRBi8;
|
|
|
|
|
case ARM::t2STRHi12: return ARM::t2STRHi8;
|
2013-09-27 01:25:10 +08:00
|
|
|
case ARM::t2PLDi12: return ARM::t2PLDi8;
|
2009-07-28 13:48:47 +08:00
|
|
|
|
|
|
|
|
case ARM::t2LDRi8:
|
|
|
|
|
case ARM::t2LDRHi8:
|
|
|
|
|
case ARM::t2LDRBi8:
|
|
|
|
|
case ARM::t2LDRSHi8:
|
|
|
|
|
case ARM::t2LDRSBi8:
|
|
|
|
|
case ARM::t2STRi8:
|
|
|
|
|
case ARM::t2STRBi8:
|
|
|
|
|
case ARM::t2STRHi8:
|
2013-09-27 01:25:10 +08:00
|
|
|
case ARM::t2PLDi8:
|
2009-07-28 13:48:47 +08:00
|
|
|
return opcode;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static unsigned
|
|
|
|
|
positiveOffsetOpcode(unsigned opcode)
|
|
|
|
|
{
|
|
|
|
|
switch (opcode) {
|
|
|
|
|
case ARM::t2LDRi8: return ARM::t2LDRi12;
|
|
|
|
|
case ARM::t2LDRHi8: return ARM::t2LDRHi12;
|
|
|
|
|
case ARM::t2LDRBi8: return ARM::t2LDRBi12;
|
|
|
|
|
case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
|
|
|
|
|
case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
|
|
|
|
|
case ARM::t2STRi8: return ARM::t2STRi12;
|
|
|
|
|
case ARM::t2STRBi8: return ARM::t2STRBi12;
|
|
|
|
|
case ARM::t2STRHi8: return ARM::t2STRHi12;
|
2013-09-27 01:25:10 +08:00
|
|
|
case ARM::t2PLDi8: return ARM::t2PLDi12;
|
2009-07-28 13:48:47 +08:00
|
|
|
|
|
|
|
|
case ARM::t2LDRi12:
|
|
|
|
|
case ARM::t2LDRHi12:
|
|
|
|
|
case ARM::t2LDRBi12:
|
|
|
|
|
case ARM::t2LDRSHi12:
|
|
|
|
|
case ARM::t2LDRSBi12:
|
|
|
|
|
case ARM::t2STRi12:
|
|
|
|
|
case ARM::t2STRBi12:
|
|
|
|
|
case ARM::t2STRHi12:
|
2013-09-27 01:25:10 +08:00
|
|
|
case ARM::t2PLDi12:
|
2009-07-28 13:48:47 +08:00
|
|
|
return opcode;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static unsigned
|
|
|
|
|
immediateOffsetOpcode(unsigned opcode)
|
|
|
|
|
{
|
|
|
|
|
switch (opcode) {
|
|
|
|
|
case ARM::t2LDRs: return ARM::t2LDRi12;
|
|
|
|
|
case ARM::t2LDRHs: return ARM::t2LDRHi12;
|
|
|
|
|
case ARM::t2LDRBs: return ARM::t2LDRBi12;
|
|
|
|
|
case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
|
|
|
|
|
case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
|
|
|
|
|
case ARM::t2STRs: return ARM::t2STRi12;
|
|
|
|
|
case ARM::t2STRBs: return ARM::t2STRBi12;
|
|
|
|
|
case ARM::t2STRHs: return ARM::t2STRHi12;
|
2013-09-27 01:25:10 +08:00
|
|
|
case ARM::t2PLDs: return ARM::t2PLDi12;
|
2009-07-28 13:48:47 +08:00
|
|
|
|
|
|
|
|
case ARM::t2LDRi12:
|
|
|
|
|
case ARM::t2LDRHi12:
|
|
|
|
|
case ARM::t2LDRBi12:
|
|
|
|
|
case ARM::t2LDRSHi12:
|
|
|
|
|
case ARM::t2LDRSBi12:
|
|
|
|
|
case ARM::t2STRi12:
|
|
|
|
|
case ARM::t2STRBi12:
|
|
|
|
|
case ARM::t2STRHi12:
|
2013-09-27 01:25:10 +08:00
|
|
|
case ARM::t2PLDi12:
|
2009-07-28 13:48:47 +08:00
|
|
|
case ARM::t2LDRi8:
|
|
|
|
|
case ARM::t2LDRHi8:
|
|
|
|
|
case ARM::t2LDRBi8:
|
|
|
|
|
case ARM::t2LDRSHi8:
|
|
|
|
|
case ARM::t2LDRSBi8:
|
|
|
|
|
case ARM::t2STRi8:
|
|
|
|
|
case ARM::t2STRBi8:
|
|
|
|
|
case ARM::t2STRHi8:
|
2013-09-27 01:25:10 +08:00
|
|
|
case ARM::t2PLDi8:
|
2009-07-28 13:48:47 +08:00
|
|
|
return opcode;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2009-08-27 09:23:50 +08:00
|
|
|
bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
|
|
|
|
|
unsigned FrameReg, int &Offset,
|
|
|
|
|
const ARMBaseInstrInfo &TII) {
|
2009-07-28 13:48:47 +08:00
|
|
|
unsigned Opcode = MI.getOpcode();
|
2011-06-29 03:10:37 +08:00
|
|
|
const MCInstrDesc &Desc = MI.getDesc();
|
2009-07-28 13:48:47 +08:00
|
|
|
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
|
|
|
|
bool isSub = false;
|
|
|
|
|
|
|
|
|
|
// Memory operands in inline assembly always use AddrModeT2_i12.
|
[ARM] additionally check for ARM::INLINEASM_BR w/ ARM::INLINEASM
Summary:
We were observing failures for arm32 allyesconfigs of the Linux kernel
with the asm goto Clang patch, where ldr's were being generated to
offsets too far away to encode in imm12.
It looks like since INLINEASM_BR was created off of INLINEASM, a few
checks for INLINEASM needed to be updated to check for either case.
pr/41999
Link: https://github.com/ClangBuiltLinux/linux/issues/490
Reviewers: peter.smith, kristof.beyls, ostannard, rengolin, t.p.northover
Reviewed By: peter.smith
Subscribers: jyu2, javed.absar, hiraditya, llvm-commits, nathanchance, craig.topper, kees, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62400
llvm-svn: 361659
2019-05-25 02:58:21 +08:00
|
|
|
if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
|
2009-07-28 13:48:47 +08:00
|
|
|
AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
|
2009-08-11 23:33:49 +08:00
|
|
|
|
2009-07-28 13:48:47 +08:00
|
|
|
if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
|
|
|
|
|
Offset += MI.getOperand(FrameRegIdx+1).getImm();
|
2009-08-07 08:34:42 +08:00
|
|
|
|
2010-01-20 05:08:28 +08:00
|
|
|
unsigned PredReg;
|
2018-02-28 03:00:59 +08:00
|
|
|
if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL &&
|
|
|
|
|
!MI.definesRegister(ARM::CPSR)) {
|
2009-07-28 13:48:47 +08:00
|
|
|
// Turn it into a move.
|
2011-07-01 07:38:17 +08:00
|
|
|
MI.setDesc(TII.get(ARM::tMOVr));
|
2009-07-28 13:48:47 +08:00
|
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
2010-01-20 05:08:28 +08:00
|
|
|
// Remove offset and remaining explicit predicate operands.
|
|
|
|
|
do MI.RemoveOperand(FrameRegIdx+1);
|
2011-07-01 06:10:46 +08:00
|
|
|
while (MI.getNumOperands() > FrameRegIdx+1);
|
2012-12-20 05:31:56 +08:00
|
|
|
MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
|
2017-01-13 17:37:56 +08:00
|
|
|
MIB.add(predOps(ARMCC::AL));
|
2009-08-27 09:23:50 +08:00
|
|
|
return true;
|
2009-07-28 13:48:47 +08:00
|
|
|
}
|
|
|
|
|
|
2010-03-09 06:56:15 +08:00
|
|
|
bool HasCCOut = Opcode != ARM::t2ADDri12;
|
|
|
|
|
|
2009-07-28 13:48:47 +08:00
|
|
|
if (Offset < 0) {
|
|
|
|
|
Offset = -Offset;
|
|
|
|
|
isSub = true;
|
2011-06-30 07:25:04 +08:00
|
|
|
MI.setDesc(TII.get(ARM::t2SUBri));
|
2009-08-07 08:34:42 +08:00
|
|
|
} else {
|
2011-06-30 07:25:04 +08:00
|
|
|
MI.setDesc(TII.get(ARM::t2ADDri));
|
2009-07-28 13:48:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Common case: small offset, fits into instruction.
|
|
|
|
|
if (ARM_AM::getT2SOImmVal(Offset) != -1) {
|
|
|
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
|
|
|
|
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
|
2010-03-09 06:56:15 +08:00
|
|
|
// Add cc_out operand if the original instruction did not have one.
|
|
|
|
|
if (!HasCCOut)
|
|
|
|
|
MI.addOperand(MachineOperand::CreateReg(0, false));
|
2009-08-27 09:23:50 +08:00
|
|
|
Offset = 0;
|
|
|
|
|
return true;
|
2009-07-28 13:48:47 +08:00
|
|
|
}
|
|
|
|
|
// Another common case: imm12.
|
2010-03-09 06:56:15 +08:00
|
|
|
if (Offset < 4096 &&
|
|
|
|
|
(!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
|
2011-06-30 07:25:04 +08:00
|
|
|
unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
|
2009-08-07 08:34:42 +08:00
|
|
|
MI.setDesc(TII.get(NewOpc));
|
2009-07-28 13:48:47 +08:00
|
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
|
|
|
|
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
|
2010-03-09 06:56:15 +08:00
|
|
|
// Remove the cc_out operand.
|
|
|
|
|
if (HasCCOut)
|
|
|
|
|
MI.RemoveOperand(MI.getNumOperands()-1);
|
2009-08-27 09:23:50 +08:00
|
|
|
Offset = 0;
|
|
|
|
|
return true;
|
2009-07-28 13:48:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Otherwise, extract 8 adjacent bits from the immediate into this
|
|
|
|
|
// t2ADDri/t2SUBri.
|
2013-05-25 06:23:49 +08:00
|
|
|
unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
|
2009-07-28 13:48:47 +08:00
|
|
|
unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
|
|
|
|
|
|
|
|
|
|
// We will handle these bits from offset, clear them.
|
|
|
|
|
Offset &= ~ThisImmVal;
|
|
|
|
|
|
|
|
|
|
assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
|
|
|
|
|
"Bit extraction didn't work?");
|
|
|
|
|
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
|
2010-03-09 06:56:15 +08:00
|
|
|
// Add cc_out operand if the original instruction did not have one.
|
|
|
|
|
if (!HasCCOut)
|
|
|
|
|
MI.addOperand(MachineOperand::CreateReg(0, false));
|
2009-07-28 13:48:47 +08:00
|
|
|
} else {
|
2010-02-06 08:24:38 +08:00
|
|
|
// AddrMode4 and AddrMode6 cannot handle any offset.
|
|
|
|
|
if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
|
2009-09-16 01:56:18 +08:00
|
|
|
return false;
|
|
|
|
|
|
2009-07-28 13:48:47 +08:00
|
|
|
// AddrModeT2_so cannot handle any offset. If there is no offset
|
|
|
|
|
// register then we change to an immediate version.
|
2009-08-07 08:34:42 +08:00
|
|
|
unsigned NewOpc = Opcode;
|
2009-07-28 13:48:47 +08:00
|
|
|
if (AddrMode == ARMII::AddrModeT2_so) {
|
|
|
|
|
unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
|
|
|
|
|
if (OffsetReg != 0) {
|
|
|
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
2009-08-27 09:23:50 +08:00
|
|
|
return Offset == 0;
|
2009-07-28 13:48:47 +08:00
|
|
|
}
|
2009-08-11 23:33:49 +08:00
|
|
|
|
2009-07-28 13:48:47 +08:00
|
|
|
MI.RemoveOperand(FrameRegIdx+1);
|
|
|
|
|
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
|
|
|
|
|
NewOpc = immediateOffsetOpcode(Opcode);
|
|
|
|
|
AddrMode = ARMII::AddrModeT2_i12;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned NumBits = 0;
|
|
|
|
|
unsigned Scale = 1;
|
|
|
|
|
if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
|
|
|
|
|
// i8 supports only negative, and i12 supports only positive, so
|
|
|
|
|
// based on Offset sign convert Opcode to the appropriate
|
|
|
|
|
// instruction
|
|
|
|
|
Offset += MI.getOperand(FrameRegIdx+1).getImm();
|
|
|
|
|
if (Offset < 0) {
|
|
|
|
|
NewOpc = negativeOffsetOpcode(Opcode);
|
|
|
|
|
NumBits = 8;
|
|
|
|
|
isSub = true;
|
|
|
|
|
Offset = -Offset;
|
|
|
|
|
} else {
|
|
|
|
|
NewOpc = positiveOffsetOpcode(Opcode);
|
|
|
|
|
NumBits = 12;
|
|
|
|
|
}
|
2010-02-06 08:24:38 +08:00
|
|
|
} else if (AddrMode == ARMII::AddrMode5) {
|
|
|
|
|
// VFP address mode.
|
|
|
|
|
const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
|
|
|
|
|
int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
|
|
|
|
|
if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
|
|
|
|
|
InstrOffs *= -1;
|
2009-07-28 13:48:47 +08:00
|
|
|
NumBits = 8;
|
|
|
|
|
Scale = 4;
|
|
|
|
|
Offset += InstrOffs * 4;
|
|
|
|
|
assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
|
|
|
|
|
if (Offset < 0) {
|
2018-02-13 18:29:03 +08:00
|
|
|
Offset = -Offset;
|
|
|
|
|
isSub = true;
|
|
|
|
|
}
|
|
|
|
|
} else if (AddrMode == ARMII::AddrMode5FP16) {
|
|
|
|
|
// VFP address mode.
|
|
|
|
|
const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
|
|
|
|
|
int InstrOffs = ARM_AM::getAM5FP16Offset(OffOp.getImm());
|
|
|
|
|
if (ARM_AM::getAM5FP16Op(OffOp.getImm()) == ARM_AM::sub)
|
|
|
|
|
InstrOffs *= -1;
|
|
|
|
|
NumBits = 8;
|
|
|
|
|
Scale = 2;
|
|
|
|
|
Offset += InstrOffs * 2;
|
|
|
|
|
assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
|
|
|
|
|
if (Offset < 0) {
|
2009-07-28 13:48:47 +08:00
|
|
|
Offset = -Offset;
|
|
|
|
|
isSub = true;
|
|
|
|
|
}
|
[ARM] Add MVE vector load/store instructions.
This adds the rest of the vector memory access instructions. It
includes contiguous loads/stores, with an ordinary addressing mode
such as [r0,#offset] (plus writeback variants); gather loads and
scatter stores with a scalar base address register and a vector of
offsets from it (written [r0,q1] or similar); and gather/scatters with
a vector of base addresses (written [q0,#offset], again with
writeback). Additionally, some of the loads can widen each loaded
value into a larger vector lane, and the corresponding stores narrow
them again.
To implement these, we also have to add the addressing modes they
need. Also, in AsmParser, the `isMem` query function now has
subqueries `isGPRMem` and `isMVEMem`, according to which kind of base
register is used by a given memory access operand.
I've also had to add an extra check in `checkTargetMatchPredicate` in
the AsmParser, without which our last-minute check of `rGPR` register
operands against SP and PC was failing an assertion because Tablegen
had inserted an immediate 0 in place of one of a pair of tied register
operands. (This matches the way the corresponding check for `MCK_rGPR`
in `validateTargetOperandClass` is guarded.) Apparently the MVE load
instructions were the first to have ever triggered this assertion, but
I think only because they were the first to have a combination of the
usual Arm pre/post writeback system and the `rGPR` class in particular.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62680
llvm-svn: 364291
2019-06-25 19:24:18 +08:00
|
|
|
} else if (AddrMode == ARMII::AddrModeT2_i7s4 ||
|
|
|
|
|
AddrMode == ARMII::AddrModeT2_i7s2 ||
|
|
|
|
|
AddrMode == ARMII::AddrModeT2_i7) {
|
[ARM] Add the non-MVE instructions in Arm v8.1-M.
This adds support for the new family of conditional selection /
increment / negation instructions; the low-overhead branch
instructions (e.g. BF, WLS, DLS); the CLRM instruction to zero a whole
list of registers at once; the new VMRS/VMSR and VLDR/VSTR
instructions to get data in and out of 8.1-M system registers,
particularly including the new VPR register used by MVE vector
predication.
To support this, we also add a register name 'zr' (used by the CSEL
family to force one of the inputs to the constant 0), and operand
types for lists of registers that are also allowed to include APSR or
VPR (used by CLRM). The VLDR/VSTR instructions also need a new
addressing mode.
The low-overhead branch instructions exist in their own separate
architecture extension, which we treat as enabled by default, but you
can say -mattr=-lob or equivalent to turn it off.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Reviewed By: samparker
Subscribers: miyuki, javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62667
llvm-svn: 363039
2019-06-11 17:29:18 +08:00
|
|
|
Offset += MI.getOperand(FrameRegIdx + 1).getImm();
|
[ARM] Add MVE vector load/store instructions.
This adds the rest of the vector memory access instructions. It
includes contiguous loads/stores, with an ordinary addressing mode
such as [r0,#offset] (plus writeback variants); gather loads and
scatter stores with a scalar base address register and a vector of
offsets from it (written [r0,q1] or similar); and gather/scatters with
a vector of base addresses (written [q0,#offset], again with
writeback). Additionally, some of the loads can widen each loaded
value into a larger vector lane, and the corresponding stores narrow
them again.
To implement these, we also have to add the addressing modes they
need. Also, in AsmParser, the `isMem` query function now has
subqueries `isGPRMem` and `isMVEMem`, according to which kind of base
register is used by a given memory access operand.
I've also had to add an extra check in `checkTargetMatchPredicate` in
the AsmParser, without which our last-minute check of `rGPR` register
operands against SP and PC was failing an assertion because Tablegen
had inserted an immediate 0 in place of one of a pair of tied register
operands. (This matches the way the corresponding check for `MCK_rGPR`
in `validateTargetOperandClass` is guarded.) Apparently the MVE load
instructions were the first to have ever triggered this assertion, but
I think only because they were the first to have a combination of the
usual Arm pre/post writeback system and the `rGPR` class in particular.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62680
llvm-svn: 364291
2019-06-25 19:24:18 +08:00
|
|
|
unsigned OffsetMask;
|
|
|
|
|
switch (AddrMode) {
|
|
|
|
|
case ARMII::AddrModeT2_i7s4: NumBits = 9; OffsetMask = 0x3; break;
|
|
|
|
|
case ARMII::AddrModeT2_i7s2: NumBits = 8; OffsetMask = 0x1; break;
|
|
|
|
|
default: NumBits = 7; OffsetMask = 0x0; break;
|
|
|
|
|
}
|
[ARM] Add the non-MVE instructions in Arm v8.1-M.
This adds support for the new family of conditional selection /
increment / negation instructions; the low-overhead branch
instructions (e.g. BF, WLS, DLS); the CLRM instruction to zero a whole
list of registers at once; the new VMRS/VMSR and VLDR/VSTR
instructions to get data in and out of 8.1-M system registers,
particularly including the new VPR register used by MVE vector
predication.
To support this, we also add a register name 'zr' (used by the CSEL
family to force one of the inputs to the constant 0), and operand
types for lists of registers that are also allowed to include APSR or
VPR (used by CLRM). The VLDR/VSTR instructions also need a new
addressing mode.
The low-overhead branch instructions exist in their own separate
architecture extension, which we treat as enabled by default, but you
can say -mattr=-lob or equivalent to turn it off.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Reviewed By: samparker
Subscribers: miyuki, javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62667
llvm-svn: 363039
2019-06-11 17:29:18 +08:00
|
|
|
// MCInst operand expects already scaled value.
|
|
|
|
|
Scale = 1;
|
|
|
|
|
assert((Offset & OffsetMask) == 0 && "Can't encode this offset!");
|
2019-06-11 18:09:12 +08:00
|
|
|
(void)OffsetMask; // squash unused-variable warning at -NDEBUG
|
2013-04-21 19:57:07 +08:00
|
|
|
} else if (AddrMode == ARMII::AddrModeT2_i8s4) {
|
|
|
|
|
Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
|
[ARM] Add MVE vector load/store instructions.
This adds the rest of the vector memory access instructions. It
includes contiguous loads/stores, with an ordinary addressing mode
such as [r0,#offset] (plus writeback variants); gather loads and
scatter stores with a scalar base address register and a vector of
offsets from it (written [r0,q1] or similar); and gather/scatters with
a vector of base addresses (written [q0,#offset], again with
writeback). Additionally, some of the loads can widen each loaded
value into a larger vector lane, and the corresponding stores narrow
them again.
To implement these, we also have to add the addressing modes they
need. Also, in AsmParser, the `isMem` query function now has
subqueries `isGPRMem` and `isMVEMem`, according to which kind of base
register is used by a given memory access operand.
I've also had to add an extra check in `checkTargetMatchPredicate` in
the AsmParser, without which our last-minute check of `rGPR` register
operands against SP and PC was failing an assertion because Tablegen
had inserted an immediate 0 in place of one of a pair of tied register
operands. (This matches the way the corresponding check for `MCK_rGPR`
in `validateTargetOperandClass` is guarded.) Apparently the MVE load
instructions were the first to have ever triggered this assertion, but
I think only because they were the first to have a combination of the
usual Arm pre/post writeback system and the `rGPR` class in particular.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62680
llvm-svn: 364291
2019-06-25 19:24:18 +08:00
|
|
|
NumBits = 8 + 2;
|
2015-02-24 09:37:31 +08:00
|
|
|
// MCInst operand expects already scaled value.
|
2013-04-21 19:57:07 +08:00
|
|
|
Scale = 1;
|
2015-02-24 09:37:31 +08:00
|
|
|
assert((Offset & 3) == 0 && "Can't encode this offset!");
|
2018-09-07 17:21:25 +08:00
|
|
|
} else if (AddrMode == ARMII::AddrModeT2_ldrex) {
|
|
|
|
|
Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
|
|
|
|
|
NumBits = 8; // 8 bits scaled by 4
|
|
|
|
|
Scale = 4;
|
|
|
|
|
assert((Offset & 3) == 0 && "Can't encode this offset!");
|
2010-02-06 08:24:38 +08:00
|
|
|
} else {
|
|
|
|
|
llvm_unreachable("Unsupported addressing mode!");
|
2009-07-28 13:48:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (NewOpc != Opcode)
|
|
|
|
|
MI.setDesc(TII.get(NewOpc));
|
|
|
|
|
|
|
|
|
|
MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
|
|
|
|
|
|
|
|
|
|
// Attempt to fold address computation
|
|
|
|
|
// Common case: small offset, fits into instruction.
|
|
|
|
|
int ImmedOffset = Offset / Scale;
|
|
|
|
|
unsigned Mask = (1 << NumBits) - 1;
|
|
|
|
|
if ((unsigned)Offset <= Mask * Scale) {
|
|
|
|
|
// Replace the FrameIndex with fp/sp
|
|
|
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
|
|
|
|
if (isSub) {
|
2019-03-01 22:20:28 +08:00
|
|
|
if (AddrMode == ARMII::AddrMode5 || AddrMode == ARMII::AddrMode5FP16)
|
2009-07-28 13:48:47 +08:00
|
|
|
// FIXME: Not consistent.
|
|
|
|
|
ImmedOffset |= 1 << NumBits;
|
2009-08-11 23:33:49 +08:00
|
|
|
else
|
2009-07-28 13:48:47 +08:00
|
|
|
ImmedOffset = -ImmedOffset;
|
|
|
|
|
}
|
|
|
|
|
ImmOp.ChangeToImmediate(ImmedOffset);
|
2009-08-27 09:23:50 +08:00
|
|
|
Offset = 0;
|
|
|
|
|
return true;
|
2009-07-28 13:48:47 +08:00
|
|
|
}
|
2009-08-11 23:33:49 +08:00
|
|
|
|
2009-07-28 13:48:47 +08:00
|
|
|
// Otherwise, offset doesn't fit. Pull in what we can to simplify
|
2009-07-29 07:52:33 +08:00
|
|
|
ImmedOffset = ImmedOffset & Mask;
|
2009-07-28 13:48:47 +08:00
|
|
|
if (isSub) {
|
2019-03-01 22:20:28 +08:00
|
|
|
if (AddrMode == ARMII::AddrMode5 || AddrMode == ARMII::AddrMode5FP16)
|
2009-07-28 13:48:47 +08:00
|
|
|
// FIXME: Not consistent.
|
|
|
|
|
ImmedOffset |= 1 << NumBits;
|
2009-08-03 10:38:06 +08:00
|
|
|
else {
|
2009-07-28 13:48:47 +08:00
|
|
|
ImmedOffset = -ImmedOffset;
|
2009-08-03 10:38:06 +08:00
|
|
|
if (ImmedOffset == 0)
|
|
|
|
|
// Change the opcode back if the encoded offset is zero.
|
|
|
|
|
MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
|
|
|
|
|
}
|
2009-07-28 13:48:47 +08:00
|
|
|
}
|
|
|
|
|
ImmOp.ChangeToImmediate(ImmedOffset);
|
|
|
|
|
Offset &= ~(Mask*Scale);
|
|
|
|
|
}
|
|
|
|
|
|
2009-08-27 09:23:50 +08:00
|
|
|
Offset = (isSub) ? -Offset : Offset;
|
|
|
|
|
return Offset == 0;
|
2009-07-28 13:48:47 +08:00
|
|
|
}
|
2010-06-10 03:26:01 +08:00
|
|
|
|
2016-02-23 10:46:52 +08:00
|
|
|
ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI,
|
|
|
|
|
unsigned &PredReg) {
|
|
|
|
|
unsigned Opc = MI.getOpcode();
|
2010-06-22 09:18:16 +08:00
|
|
|
if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
|
|
|
|
|
return ARMCC::AL;
|
2012-03-27 15:21:54 +08:00
|
|
|
return getInstrPredicate(MI, PredReg);
|
2010-06-22 09:18:16 +08:00
|
|
|
}
|
2019-06-14 19:46:05 +08:00
|
|
|
|
|
|
|
|
int llvm::findFirstVPTPredOperandIdx(const MachineInstr &MI) {
|
|
|
|
|
const MCInstrDesc &MCID = MI.getDesc();
|
|
|
|
|
|
|
|
|
|
if (!MCID.OpInfo)
|
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
|
|
|
|
|
if (ARM::isVpred(MCID.OpInfo[i].OperandType))
|
|
|
|
|
return i;
|
|
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ARMVCC::VPTCodes llvm::getVPTInstrPredicate(const MachineInstr &MI,
|
|
|
|
|
unsigned &PredReg) {
|
|
|
|
|
int PIdx = findFirstVPTPredOperandIdx(MI);
|
|
|
|
|
if (PIdx == -1) {
|
|
|
|
|
PredReg = 0;
|
|
|
|
|
return ARMVCC::None;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
PredReg = MI.getOperand(PIdx+1).getReg();
|
|
|
|
|
return (ARMVCC::VPTCodes)MI.getOperand(PIdx).getImm();
|
|
|
|
|
}
|