2012-12-12 05:25:42 +08:00
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//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2012-12-12 05:25:42 +08:00
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//
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/// \file
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//===----------------------------------------------------------------------===//
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2016-03-11 16:00:27 +08:00
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
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2012-12-12 05:25:42 +08:00
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2016-10-04 02:47:26 +08:00
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#include "llvm/Target/TargetMachine.h"
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2019-12-11 23:55:26 +08:00
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#include "llvm/IR/IntrinsicsR600.h" // TODO: Sink this.
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#include "llvm/IR/IntrinsicsAMDGPU.h" // TODO: Sink this.
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2016-10-04 02:47:26 +08:00
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2012-12-12 05:25:42 +08:00
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namespace llvm {
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class AMDGPUTargetMachine;
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2013-06-08 04:37:48 +08:00
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class FunctionPass;
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2016-07-20 07:16:53 +08:00
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class GCNTargetMachine;
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2016-08-12 03:18:50 +08:00
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class ModulePass;
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class Pass;
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2013-06-08 04:37:48 +08:00
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class Target;
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class TargetMachine;
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2017-09-30 07:40:19 +08:00
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class TargetOptions;
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2016-08-12 03:18:50 +08:00
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class PassRegistry;
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2017-03-27 22:04:01 +08:00
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class Module;
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2012-12-12 05:25:42 +08:00
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2020-01-06 01:22:21 +08:00
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// GlobalISel passes
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void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
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FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
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2020-02-18 00:47:45 +08:00
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void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
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FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
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2020-01-06 01:22:21 +08:00
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2012-12-12 05:25:42 +08:00
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// R600 Passes
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2017-05-19 01:21:13 +08:00
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FunctionPass *createR600VectorRegMerger();
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FunctionPass *createR600ExpandSpecialInstrsPass();
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2013-12-12 01:51:41 +08:00
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FunctionPass *createR600EmitClauseMarkers();
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2017-05-19 01:21:13 +08:00
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FunctionPass *createR600ClauseMergePass();
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FunctionPass *createR600Packetizer();
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FunctionPass *createR600ControlFlowFinalizer();
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2013-12-12 01:51:47 +08:00
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FunctionPass *createAMDGPUCFGStructurizerPass();
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2017-08-08 12:57:55 +08:00
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FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
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2012-12-12 05:25:42 +08:00
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// SI Passes
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2018-11-30 22:21:56 +08:00
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FunctionPass *createGCNDPPCombinePass();
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2012-12-20 06:10:31 +08:00
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FunctionPass *createSIAnnotateControlFlowPass();
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2014-11-22 06:06:37 +08:00
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FunctionPass *createSIFoldOperandsPass();
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[ADMGPU] SDWA peephole optimization pass.
Summary:
First iteration of SDWA peephole.
This pass tries to combine several instruction into one SDWA instruction. E.g. it converts:
'''
V_LSHRREV_B32_e32 %vreg0, 16, %vreg1
V_ADD_I32_e32 %vreg2, %vreg0, %vreg3
V_LSHLREV_B32_e32 %vreg4, 16, %vreg2
'''
Into:
'''
V_ADD_I32_sdwa %vreg4, %vreg1, %vreg3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
'''
Pass structure:
1. Iterate over machine instruction in basic block and try to apply "SDWA patterns" to each of them. SDWA patterns match machine instruction into either source or destination SDWA operand. E.g. ''' V_LSHRREV_B32_e32 %vreg0, 16, %vreg1''' is matched to source SDWA operand '''%vreg1 src_sel:WORD_1'''.
2. Iterate over found SDWA operands and find instruction that could be potentially coverted into SDWA. E.g. for source SDWA operand potential instruction are all instruction in this basic block that uses '''%vreg0'''
3. Iterate over all potential instructions and check if they can be converted into SDWA.
4. Convert instructions to SDWA.
This review contains basic implementation of SDWA peephole pass. This pass requires additional testing fot both correctness and performance (no performance testing done).
There are several ways this pass can be improved:
1. Make this pass work on whole function not only basic block. As I can see this can be done right now without changes to pass.
2. Introduce more SDWA patterns
3. Introduce mnemonics to limit when SDWA patterns should apply
Reviewers: vpykhtin, alex-t, arsenm, rampitec
Subscribers: wdng, nhaehnle, mgorny
Differential Revision: https://reviews.llvm.org/D30038
llvm-svn: 298365
2017-03-21 20:51:34 +08:00
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FunctionPass *createSIPeepholeSDWAPass();
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2014-04-30 23:31:33 +08:00
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FunctionPass *createSILowerI1CopiesPass();
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2018-11-16 09:13:34 +08:00
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FunctionPass *createSIFixupVectorISelPass();
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[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
TFE and LWE support requires extra result registers that are written in the
event of a failure in order to detect that failure case.
The specific use-case that initiated these changes is sparse texture support.
This means that if image intrinsics are used with either option turned on, the
programmer must ensure that the return type can contain all of the expected
results. This can result in redundant registers since the vector size must be a
power-of-2.
This change takes roughly 6 parts:
1. Modify the instruction defs in tablegen to add new instruction variants that
can accomodate the extra return values.
2. Updates to lowerImage in SIISelLowering.cpp to accomodate setting TFE or LWE
(where the bulk of the work for these instruction types is now done)
3. Extra verification code to catch cases where intrinsics have been used but
insufficient return registers are used.
4. Modification to the adjustWritemask optimisation to account for TFE/LWE being
enabled (requires extra registers to be maintained for error return value).
5. An extra pass to zero initialize the error value return - this is because if
the error does not occur, the register is not written and thus must be zeroed
before use. Also added a new (on by default) option to ensure ALL return values
are zero-initialized that is required for sparse texture support.
6. Disable the inst_combine optimization in the presence of tfe/lwe (later TODO
for this to re-enable and handle correctly).
There's an additional fix now to avoid a dmask=0
For an image intrinsic with tfe where all result channels except tfe
were unused, I was getting an image instruction with dmask=0 and only a
single vgpr result for tfe. That is incorrect because the hardware
assumes there is at least one vgpr result, plus the one for tfe.
Fixed by forcing dmask to 1, which gives the desired two vgpr result
with tfe in the second one.
The TFE or LWE result is returned from the intrinsics using an aggregate
type. Look in the test code provided to see how this works, but in essence IR
code to invoke the intrinsic looks as follows:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 15,
i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
%v.err = extractvalue {<4 x float>, i32} %v, 1
This re-submit of the change also includes a slight modification in
SIISelLowering.cpp to work-around a compiler bug for the powerpc_le
platform that caused a buildbot failure on a previous submission.
Differential revision: https://reviews.llvm.org/D48826
Change-Id: If222bc03642e76cf98059a6bef5d5bffeda38dda
Work around for ppcle compiler bug
Change-Id: Ie284cf24b2271215be1b9dc95b485fd15000e32b
llvm-svn: 351054
2019-01-14 19:55:24 +08:00
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FunctionPass *createSIAddIMGInitPass();
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2014-07-22 00:55:33 +08:00
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FunctionPass *createSIShrinkInstructionsPass();
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2017-05-19 01:21:13 +08:00
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FunctionPass *createSILoadStoreOptimizerPass();
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2016-03-22 04:28:33 +08:00
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FunctionPass *createSIWholeQuadModePass();
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2015-05-13 01:13:02 +08:00
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FunctionPass *createSIFixControlFlowLiveIntervalsPass();
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2017-08-02 07:14:32 +08:00
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FunctionPass *createSIOptimizeExecMaskingPreRAPass();
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2015-11-04 06:30:13 +08:00
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FunctionPass *createSIFixSGPRCopiesPass();
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2017-07-22 05:19:23 +08:00
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FunctionPass *createSIMemoryLegalizerPass();
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2017-04-12 11:25:12 +08:00
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FunctionPass *createSIInsertWaitcntsPass();
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2019-04-01 23:19:52 +08:00
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FunctionPass *createSIPreAllocateWWMRegsPass();
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2018-06-01 04:13:51 +08:00
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FunctionPass *createSIFormMemoryClausesPass();
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2019-12-05 17:45:32 +08:00
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2020-01-14 06:54:17 +08:00
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FunctionPass *createSIPostRABundlerPass();
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2019-12-05 17:45:32 +08:00
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FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *);
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2017-08-12 00:42:09 +08:00
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FunctionPass *createAMDGPUUseNativeCallsPass();
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2017-05-19 01:21:13 +08:00
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FunctionPass *createAMDGPUCodeGenPreparePass();
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2017-05-16 04:18:37 +08:00
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FunctionPass *createAMDGPUMachineCFGStructurizerPass();
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2019-06-18 01:47:28 +08:00
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FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *);
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ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *);
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2017-07-29 02:40:05 +08:00
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FunctionPass *createAMDGPURewriteOutArgumentsPass();
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2018-12-10 20:06:10 +08:00
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FunctionPass *createSIModeRegisterPass();
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2017-05-16 04:18:37 +08:00
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2017-08-04 06:30:46 +08:00
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void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
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2017-05-16 04:18:37 +08:00
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void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
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extern char &AMDGPUMachineCFGStructurizerID;
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2012-12-12 05:25:42 +08:00
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2017-06-03 02:02:42 +08:00
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void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
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2017-07-14 05:43:42 +08:00
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Pass *createAMDGPUAnnotateKernelFeaturesPass();
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2015-11-07 02:01:57 +08:00
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void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
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extern char &AMDGPUAnnotateKernelFeaturesID;
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2018-10-08 23:49:19 +08:00
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FunctionPass *createAMDGPUAtomicOptimizerPass();
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void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
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extern char &AMDGPUAtomicOptimizerID;
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2017-05-19 01:21:13 +08:00
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ModulePass *createAMDGPULowerIntrinsicsPass();
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2017-02-10 06:00:42 +08:00
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void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
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extern char &AMDGPULowerIntrinsicsID;
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2018-10-26 21:18:36 +08:00
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ModulePass *createAMDGPUFixFunctionBitcastsPass();
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void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &);
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extern char &AMDGPUFixFunctionBitcastsID;
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AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
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FunctionPass *createAMDGPULowerKernelArgumentsPass();
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void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
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extern char &AMDGPULowerKernelArgumentsID;
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2018-05-19 05:35:00 +08:00
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ModulePass *createAMDGPULowerKernelAttributesPass();
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void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
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extern char &AMDGPULowerKernelAttributesID;
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2019-06-18 01:47:28 +08:00
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void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &);
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extern char &AMDGPUPropagateAttributesEarlyID;
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void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &);
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extern char &AMDGPUPropagateAttributesLateID;
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2017-07-29 02:40:05 +08:00
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void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
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extern char &AMDGPURewriteOutArgumentsID;
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2018-11-30 22:21:56 +08:00
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void initializeGCNDPPCombinePass(PassRegistry &);
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extern char &GCNDPPCombineID;
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2017-08-03 06:19:45 +08:00
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void initializeR600ClauseMergePassPass(PassRegistry &);
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extern char &R600ClauseMergePassID;
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void initializeR600ControlFlowFinalizerPass(PassRegistry &);
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extern char &R600ControlFlowFinalizerID;
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void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
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extern char &R600ExpandSpecialInstrsPassID;
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void initializeR600VectorRegMergerPass(PassRegistry &);
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extern char &R600VectorRegMergerID;
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void initializeR600PacketizerPass(PassRegistry &);
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extern char &R600PacketizerID;
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2014-11-22 06:06:37 +08:00
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void initializeSIFoldOperandsPass(PassRegistry &);
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extern char &SIFoldOperandsID;
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[ADMGPU] SDWA peephole optimization pass.
Summary:
First iteration of SDWA peephole.
This pass tries to combine several instruction into one SDWA instruction. E.g. it converts:
'''
V_LSHRREV_B32_e32 %vreg0, 16, %vreg1
V_ADD_I32_e32 %vreg2, %vreg0, %vreg3
V_LSHLREV_B32_e32 %vreg4, 16, %vreg2
'''
Into:
'''
V_ADD_I32_sdwa %vreg4, %vreg1, %vreg3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
'''
Pass structure:
1. Iterate over machine instruction in basic block and try to apply "SDWA patterns" to each of them. SDWA patterns match machine instruction into either source or destination SDWA operand. E.g. ''' V_LSHRREV_B32_e32 %vreg0, 16, %vreg1''' is matched to source SDWA operand '''%vreg1 src_sel:WORD_1'''.
2. Iterate over found SDWA operands and find instruction that could be potentially coverted into SDWA. E.g. for source SDWA operand potential instruction are all instruction in this basic block that uses '''%vreg0'''
3. Iterate over all potential instructions and check if they can be converted into SDWA.
4. Convert instructions to SDWA.
This review contains basic implementation of SDWA peephole pass. This pass requires additional testing fot both correctness and performance (no performance testing done).
There are several ways this pass can be improved:
1. Make this pass work on whole function not only basic block. As I can see this can be done right now without changes to pass.
2. Introduce more SDWA patterns
3. Introduce mnemonics to limit when SDWA patterns should apply
Reviewers: vpykhtin, alex-t, arsenm, rampitec
Subscribers: wdng, nhaehnle, mgorny
Differential Revision: https://reviews.llvm.org/D30038
llvm-svn: 298365
2017-03-21 20:51:34 +08:00
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void initializeSIPeepholeSDWAPass(PassRegistry &);
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extern char &SIPeepholeSDWAID;
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2016-06-10 07:18:47 +08:00
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void initializeSIShrinkInstructionsPass(PassRegistry&);
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extern char &SIShrinkInstructionsID;
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2015-11-04 06:30:13 +08:00
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void initializeSIFixSGPRCopiesPass(PassRegistry &);
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extern char &SIFixSGPRCopiesID;
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2017-01-25 01:46:17 +08:00
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void initializeSIFixVGPRCopiesPass(PassRegistry &);
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extern char &SIFixVGPRCopiesID;
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2018-11-16 09:13:34 +08:00
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void initializeSIFixupVectorISelPass(PassRegistry &);
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extern char &SIFixupVectorISelID;
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2014-04-30 23:31:33 +08:00
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void initializeSILowerI1CopiesPass(PassRegistry &);
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extern char &SILowerI1CopiesID;
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2019-07-04 07:32:29 +08:00
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void initializeSILowerSGPRSpillsPass(PassRegistry &);
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extern char &SILowerSGPRSpillsID;
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2014-10-11 06:01:59 +08:00
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void initializeSILoadStoreOptimizerPass(PassRegistry &);
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extern char &SILoadStoreOptimizerID;
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2016-03-22 04:28:33 +08:00
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void initializeSIWholeQuadModePass(PassRegistry &);
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extern char &SIWholeQuadModeID;
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2016-02-12 10:16:10 +08:00
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void initializeSILowerControlFlowPass(PassRegistry &);
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2016-08-23 03:33:16 +08:00
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extern char &SILowerControlFlowID;
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2016-02-12 10:16:10 +08:00
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2020-01-22 12:07:55 +08:00
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void initializeSIRemoveShortExecBranchesPass(PassRegistry &);
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extern char &SIRemoveShortExecBranchesID;
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2020-03-25 22:15:16 +08:00
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void initializeSIPreEmitPeepholePass(PassRegistry &);
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extern char &SIPreEmitPeepholeID;
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2016-08-23 03:33:16 +08:00
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void initializeSIInsertSkipsPass(PassRegistry &);
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extern char &SIInsertSkipsPassID;
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2016-02-12 10:16:10 +08:00
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2016-09-29 09:44:16 +08:00
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void initializeSIOptimizeExecMaskingPass(PassRegistry &);
|
|
|
|
|
extern char &SIOptimizeExecMaskingID;
|
|
|
|
|
|
2019-04-01 23:19:52 +08:00
|
|
|
void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
|
|
|
|
|
extern char &SIPreAllocateWWMRegsID;
|
[AMDGPU] Add support for Whole Wavefront Mode
Summary:
Whole Wavefront Wode (WWM) is similar to WQM, except that all of the
lanes are always enabled, regardless of control flow. This is required
for implementing wavefront reductions in non-uniform control flow, where
we need to use the inactive lanes to propagate intermediate results, so
they need to be enabled. We need to propagate WWM to uses (unless
they're explicitly marked as exact) so that they also propagate
intermediate results correctly. We do the analysis and exec mask munging
during the WQM pass, since there are interactions with WQM for things
that require both WQM and WWM. For simplicity, WWM is entirely
block-local -- blocks are never WWM on entry or exit of a block, and WWM
is not propagated to the block level. This means that computations
involving WWM cannot involve control flow, but we only ever plan to use
WWM for a few limited purposes (none of which involve control flow)
anyways.
Shaders can ask for WWM using the @llvm.amdgcn.wwm intrinsic. There
isn't yet a way to turn WWM off -- that will be added in a future
change.
Finally, it turns out that turning on inactive lanes causes a number of
problems with register allocation. While the best long-term solution
seems like teaching LLVM's register allocator about predication, for now
we need to add some hacks to prevent ourselves from getting into trouble
due to constraints that aren't currently expressed in LLVM. For the gory
details, see the comments at the top of SIFixWWMLiveness.cpp.
Reviewers: arsenm, nhaehnle, tpr
Subscribers: kzhuravl, wdng, mgorny, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D35524
llvm-svn: 310087
2017-08-05 02:36:52 +08:00
|
|
|
|
2017-08-12 00:42:09 +08:00
|
|
|
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
|
|
|
|
|
extern char &AMDGPUSimplifyLibCallsID;
|
|
|
|
|
|
|
|
|
|
void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
|
|
|
|
|
extern char &AMDGPUUseNativeCallsID;
|
|
|
|
|
|
[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
TFE and LWE support requires extra result registers that are written in the
event of a failure in order to detect that failure case.
The specific use-case that initiated these changes is sparse texture support.
This means that if image intrinsics are used with either option turned on, the
programmer must ensure that the return type can contain all of the expected
results. This can result in redundant registers since the vector size must be a
power-of-2.
This change takes roughly 6 parts:
1. Modify the instruction defs in tablegen to add new instruction variants that
can accomodate the extra return values.
2. Updates to lowerImage in SIISelLowering.cpp to accomodate setting TFE or LWE
(where the bulk of the work for these instruction types is now done)
3. Extra verification code to catch cases where intrinsics have been used but
insufficient return registers are used.
4. Modification to the adjustWritemask optimisation to account for TFE/LWE being
enabled (requires extra registers to be maintained for error return value).
5. An extra pass to zero initialize the error value return - this is because if
the error does not occur, the register is not written and thus must be zeroed
before use. Also added a new (on by default) option to ensure ALL return values
are zero-initialized that is required for sparse texture support.
6. Disable the inst_combine optimization in the presence of tfe/lwe (later TODO
for this to re-enable and handle correctly).
There's an additional fix now to avoid a dmask=0
For an image intrinsic with tfe where all result channels except tfe
were unused, I was getting an image instruction with dmask=0 and only a
single vgpr result for tfe. That is incorrect because the hardware
assumes there is at least one vgpr result, plus the one for tfe.
Fixed by forcing dmask to 1, which gives the desired two vgpr result
with tfe in the second one.
The TFE or LWE result is returned from the intrinsics using an aggregate
type. Look in the test code provided to see how this works, but in essence IR
code to invoke the intrinsic looks as follows:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 15,
i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
%v.err = extractvalue {<4 x float>, i32} %v, 1
This re-submit of the change also includes a slight modification in
SIISelLowering.cpp to work-around a compiler bug for the powerpc_le
platform that caused a buildbot failure on a previous submission.
Differential revision: https://reviews.llvm.org/D48826
Change-Id: If222bc03642e76cf98059a6bef5d5bffeda38dda
Work around for ppcle compiler bug
Change-Id: Ie284cf24b2271215be1b9dc95b485fd15000e32b
llvm-svn: 351054
2019-01-14 19:55:24 +08:00
|
|
|
void initializeSIAddIMGInitPass(PassRegistry &);
|
|
|
|
|
extern char &SIAddIMGInitID;
|
|
|
|
|
|
2018-05-26 01:25:12 +08:00
|
|
|
void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
|
|
|
|
|
extern char &AMDGPUPerfHintAnalysisID;
|
|
|
|
|
|
2012-12-12 05:25:42 +08:00
|
|
|
// Passes common to R600 and SI
|
2017-05-19 01:21:13 +08:00
|
|
|
FunctionPass *createAMDGPUPromoteAlloca();
|
2016-01-30 13:19:45 +08:00
|
|
|
void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
|
|
|
|
|
extern char &AMDGPUPromoteAllocaID;
|
|
|
|
|
|
2012-12-20 06:10:31 +08:00
|
|
|
Pass *createAMDGPUStructurizeCFGPass();
|
2017-08-04 06:30:46 +08:00
|
|
|
FunctionPass *createAMDGPUISelDag(
|
|
|
|
|
TargetMachine *TM = nullptr,
|
|
|
|
|
CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
|
2017-03-31 04:16:02 +08:00
|
|
|
ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
|
2018-05-13 18:04:48 +08:00
|
|
|
ModulePass *createR600OpenCLImageTypeLoweringPass();
|
2015-12-16 04:55:55 +08:00
|
|
|
FunctionPass *createAMDGPUAnnotateUniformValues();
|
2013-06-08 04:37:48 +08:00
|
|
|
|
2019-08-13 01:12:29 +08:00
|
|
|
ModulePass *createAMDGPUPrintfRuntimeBinding();
|
|
|
|
|
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
|
|
|
|
|
extern char &AMDGPUPrintfRuntimeBindingID;
|
|
|
|
|
|
2017-01-28 00:38:10 +08:00
|
|
|
ModulePass* createAMDGPUUnifyMetadataPass();
|
2016-12-09 03:46:04 +08:00
|
|
|
void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
|
|
|
|
|
extern char &AMDGPUUnifyMetadataID;
|
|
|
|
|
|
2017-08-02 07:14:32 +08:00
|
|
|
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
|
|
|
|
|
extern char &SIOptimizeExecMaskingPreRAID;
|
|
|
|
|
|
2015-12-16 04:55:55 +08:00
|
|
|
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
|
|
|
|
|
extern char &AMDGPUAnnotateUniformValuesPassID;
|
2014-07-03 04:53:48 +08:00
|
|
|
|
2016-06-24 15:07:55 +08:00
|
|
|
void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
|
|
|
|
|
extern char &AMDGPUCodeGenPrepareID;
|
|
|
|
|
|
2016-01-20 23:48:27 +08:00
|
|
|
void initializeSIAnnotateControlFlowPass(PassRegistry&);
|
|
|
|
|
extern char &SIAnnotateControlFlowPassID;
|
|
|
|
|
|
2017-07-22 05:19:23 +08:00
|
|
|
void initializeSIMemoryLegalizerPass(PassRegistry&);
|
|
|
|
|
extern char &SIMemoryLegalizerID;
|
|
|
|
|
|
2018-12-10 20:06:10 +08:00
|
|
|
void initializeSIModeRegisterPass(PassRegistry&);
|
|
|
|
|
extern char &SIModeRegisterID;
|
|
|
|
|
|
2017-04-12 11:25:12 +08:00
|
|
|
void initializeSIInsertWaitcntsPass(PassRegistry&);
|
|
|
|
|
extern char &SIInsertWaitcntsID;
|
|
|
|
|
|
2018-06-01 04:13:51 +08:00
|
|
|
void initializeSIFormMemoryClausesPass(PassRegistry&);
|
|
|
|
|
extern char &SIFormMemoryClausesID;
|
|
|
|
|
|
2020-01-14 06:54:17 +08:00
|
|
|
void initializeSIPostRABundlerPass(PassRegistry&);
|
|
|
|
|
extern char &SIPostRABundlerID;
|
|
|
|
|
|
2017-03-25 03:52:05 +08:00
|
|
|
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
|
|
|
|
|
extern char &AMDGPUUnifyDivergentExitNodesID;
|
|
|
|
|
|
2017-03-18 07:56:58 +08:00
|
|
|
ImmutablePass *createAMDGPUAAWrapperPass();
|
|
|
|
|
void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
|
2018-11-08 04:26:42 +08:00
|
|
|
ImmutablePass *createAMDGPUExternalAAWrapperPass();
|
|
|
|
|
void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
|
2017-03-18 07:56:58 +08:00
|
|
|
|
2017-08-04 06:30:46 +08:00
|
|
|
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
|
|
|
|
|
|
2017-09-20 12:25:58 +08:00
|
|
|
Pass *createAMDGPUFunctionInliningPass();
|
|
|
|
|
void initializeAMDGPUInlinerPass(PassRegistry&);
|
|
|
|
|
|
2017-10-11 03:39:48 +08:00
|
|
|
ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
|
|
|
|
|
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
|
|
|
|
|
extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
|
|
|
|
|
|
2019-05-02 00:49:31 +08:00
|
|
|
void initializeGCNRegBankReassignPass(PassRegistry &);
|
|
|
|
|
extern char &GCNRegBankReassignID;
|
|
|
|
|
|
2019-05-02 00:40:49 +08:00
|
|
|
void initializeGCNNSAReassignPass(PassRegistry &);
|
|
|
|
|
extern char &GCNNSAReassignID;
|
|
|
|
|
|
2014-07-21 22:01:14 +08:00
|
|
|
namespace AMDGPU {
|
|
|
|
|
enum TargetIndex {
|
2015-01-21 01:49:47 +08:00
|
|
|
TI_CONSTDATA_START,
|
|
|
|
|
TI_SCRATCH_RSRC_DWORD0,
|
|
|
|
|
TI_SCRATCH_RSRC_DWORD1,
|
|
|
|
|
TI_SCRATCH_RSRC_DWORD2,
|
|
|
|
|
TI_SCRATCH_RSRC_DWORD3
|
2014-07-21 22:01:14 +08:00
|
|
|
};
|
|
|
|
|
}
|
|
|
|
|
|
2012-12-12 05:25:42 +08:00
|
|
|
} // End namespace llvm
|
|
|
|
|
|
2013-06-08 04:37:48 +08:00
|
|
|
/// OpenCL uses address spaces to differentiate between
|
|
|
|
|
/// various memory regions on the hardware. On the CPU
|
|
|
|
|
/// all of the address spaces point to the same memory,
|
|
|
|
|
/// however on the GPU, each address space points to
|
2014-01-25 01:20:08 +08:00
|
|
|
/// a separate piece of memory that is unique from other
|
2013-06-08 04:37:48 +08:00
|
|
|
/// memory locations.
|
2018-08-31 13:49:54 +08:00
|
|
|
namespace AMDGPUAS {
|
2017-11-01 07:21:30 +08:00
|
|
|
enum : unsigned {
|
|
|
|
|
// The maximum value for flat, generic, local, private, constant and region.
|
2019-03-18 22:44:28 +08:00
|
|
|
MAX_AMDGPU_ADDRESS = 7,
|
2017-11-01 07:21:30 +08:00
|
|
|
|
2018-08-31 13:49:54 +08:00
|
|
|
FLAT_ADDRESS = 0, ///< Address space for flat memory.
|
2017-11-01 07:21:30 +08:00
|
|
|
GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
|
2019-01-16 23:43:53 +08:00
|
|
|
REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
|
2018-08-31 13:49:54 +08:00
|
|
|
|
2019-03-18 22:44:28 +08:00
|
|
|
CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
|
2017-11-01 07:21:30 +08:00
|
|
|
LOCAL_ADDRESS = 3, ///< Address space for local memory.
|
2018-08-31 13:49:54 +08:00
|
|
|
PRIVATE_ADDRESS = 5, ///< Address space for private memory.
|
2018-02-10 00:57:57 +08:00
|
|
|
|
2019-03-18 22:44:28 +08:00
|
|
|
CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
|
2018-02-10 00:57:57 +08:00
|
|
|
|
2019-03-18 22:44:28 +08:00
|
|
|
BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
|
|
|
|
|
|
|
|
|
|
/// Address space for direct addressible parameter memory (CONST0).
|
2017-11-01 07:21:30 +08:00
|
|
|
PARAM_D_ADDRESS = 6,
|
2019-03-18 22:44:28 +08:00
|
|
|
/// Address space for indirect addressible parameter memory (VTX1).
|
2017-11-01 07:21:30 +08:00
|
|
|
PARAM_I_ADDRESS = 7,
|
|
|
|
|
|
|
|
|
|
// Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
|
|
|
|
|
// this order to be able to dynamically index a constant buffer, for
|
|
|
|
|
// example:
|
|
|
|
|
//
|
|
|
|
|
// ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
|
|
|
|
|
|
|
|
|
|
CONSTANT_BUFFER_0 = 8,
|
|
|
|
|
CONSTANT_BUFFER_1 = 9,
|
|
|
|
|
CONSTANT_BUFFER_2 = 10,
|
|
|
|
|
CONSTANT_BUFFER_3 = 11,
|
|
|
|
|
CONSTANT_BUFFER_4 = 12,
|
|
|
|
|
CONSTANT_BUFFER_5 = 13,
|
|
|
|
|
CONSTANT_BUFFER_6 = 14,
|
|
|
|
|
CONSTANT_BUFFER_7 = 15,
|
|
|
|
|
CONSTANT_BUFFER_8 = 16,
|
|
|
|
|
CONSTANT_BUFFER_9 = 17,
|
|
|
|
|
CONSTANT_BUFFER_10 = 18,
|
|
|
|
|
CONSTANT_BUFFER_11 = 19,
|
|
|
|
|
CONSTANT_BUFFER_12 = 20,
|
|
|
|
|
CONSTANT_BUFFER_13 = 21,
|
|
|
|
|
CONSTANT_BUFFER_14 = 22,
|
|
|
|
|
CONSTANT_BUFFER_15 = 23,
|
|
|
|
|
|
|
|
|
|
// Some places use this if the address space can't be determined.
|
|
|
|
|
UNKNOWN_ADDRESS_SPACE = ~0u,
|
|
|
|
|
};
|
2018-09-03 18:17:25 +08:00
|
|
|
}
|
2013-06-08 04:37:48 +08:00
|
|
|
|
2014-08-14 00:26:38 +08:00
|
|
|
#endif
|