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llvm-project/llvm/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-2...

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[Hexagon] Fix typo in HexagonEarlyIfCConv.cpp Found by PVS-Studio. Fixes llvm.org/PR32480. llvm-svn: 299258
2017-04-01 04:36:00 +08:00
; RUN: llc -march=hexagon -hexagon-eif=0 < %s | FileCheck %s
IfConversion: Fix branch predication bug. This bug shows up with diamonds that share unpredicable, unanalyzable branches. There's an included test case from Hexagon. What was happening was that we were attempting to predicate the branch instruction despite the fact that it was checked to be the same. Now for unanalyzable branches we skip over the branch instructions when predicating the block. Differential Revision: https://reviews.llvm.org/D23939 llvm-svn: 279985
2016-08-30 02:27:12 +08:00
target triple = "hexagon"
%struct.0 = type { i16, i16 }
@t = external local_unnamed_addr global %struct.0, align 2
define void @foo(i32 %p) local_unnamed_addr #0 {
entry:
%conv90 = trunc i32 %p to i16
%call105 = call signext i16 @bar(i16 signext 16384, i16 signext undef) #0
%call175 = call signext i16 @bar(i16 signext %conv90, i16 signext 4) #0
%call197 = call signext i16 @bar(i16 signext %conv90, i16 signext 4) #0
%cmp199 = icmp eq i16 %call197, 0
br i1 %cmp199, label %if.then200, label %if.else201
; CHECK-DAG: [[R4:r[0-9]+]] = #4
[Hexagon] Replace instruction definitions with auto-generated ones llvm-svn: 294753
2017-02-10 23:33:13 +08:00
; CHECK: p0 = cmp.eq(r0,#0)
IfConversion: Fix branch predication bug. This bug shows up with diamonds that share unpredicable, unanalyzable branches. There's an included test case from Hexagon. What was happening was that we were attempting to predicate the branch instruction despite the fact that it was checked to be the same. Now for unanalyzable branches we skip over the branch instructions when predicating the block. Differential Revision: https://reviews.llvm.org/D23939 llvm-svn: 279985
2016-08-30 02:27:12 +08:00
; CHECK: if (!p0.new) [[R3:r[0-9]+]] = #3
; CHECK-DAG: if (!p0) memh(##t) = [[R3]]
; CHECK-DAG: if (p0) memh(##t) = [[R4]]
if.then200: ; preds = %entry
store i16 4, i16* getelementptr inbounds (%struct.0, %struct.0* @t, i32 0, i32 0), align 2
store i16 0, i16* getelementptr inbounds (%struct.0, %struct.0* @t, i32 0, i32 1), align 2
br label %if.end202
if.else201: ; preds = %entry
store i16 3, i16* getelementptr inbounds (%struct.0, %struct.0* @t, i32 0, i32 0), align 2
br label %if.end202
if.end202: ; preds = %if.else201, %if.then200
ret void
}
declare signext i16 @bar(i16 signext, i16 signext) local_unnamed_addr #0
attributes #0 = { optsize "target-cpu"="hexagonv55" }