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llvm-project/llvm/test/CodeGen/SPARC/atomics.ll

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[Sparc] Fix "Cannot select" error for AtomicFence on 32-bit V9 Summary: This also adds testing of 32-bit V9 atomic lowering, splitting the 64-bit-only tests out into their own file. Reviewers: venkatra, jyknight Reviewed By: jyknight Subscribers: hiraditya, fedor.sergeev, jfb, llvm-commits, glaubitz Tags: #llvm Differential Revision: https://reviews.llvm.org/D69352
2019-11-18 17:45:07 +08:00
; RUN: llc < %s -march=sparc -mcpu=v9 -verify-machineinstrs | FileCheck %s
Implement atomicrmw operations in 32 and 64 bits for SPARCv9. These all use the compare-and-swap CASA/CASXA instructions. llvm-svn: 199975
2014-01-24 14:23:31 +08:00
; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s
[Sparc] Handle atomic loads/stores in sparc backend. llvm-svn: 198286
2014-01-02 06:11:54 +08:00
[SPARC] Fix 8 and 16-bit atomic load and store. They were accidentally using the 32-bit load/store instruction for 8/16-bit operations, due to incorrect patterns (8/16-bit cmpxchg and atomicrmw will be fixed in subsequent changes) llvm-svn: 270486
2016-05-24 04:33:00 +08:00
; CHECK-LABEL: test_atomic_i8
; CHECK: ldub [%o0]
; CHECK: membar
; CHECK: ldub [%o1]
; CHECK: membar
; CHECK: membar
; CHECK: stb {{.+}}, [%o2]
define i8 @test_atomic_i8(i8* %ptr1, i8* %ptr2, i8* %ptr3) {
entry:
%0 = load atomic i8, i8* %ptr1 acquire, align 1
%1 = load atomic i8, i8* %ptr2 acquire, align 1
%2 = add i8 %0, %1
store atomic i8 %2, i8* %ptr3 release, align 1
ret i8 %2
}
; CHECK-LABEL: test_atomic_i16
; CHECK: lduh [%o0]
; CHECK: membar
; CHECK: lduh [%o1]
; CHECK: membar
; CHECK: membar
; CHECK: sth {{.+}}, [%o2]
define i16 @test_atomic_i16(i16* %ptr1, i16* %ptr2, i16* %ptr3) {
entry:
%0 = load atomic i16, i16* %ptr1 acquire, align 2
%1 = load atomic i16, i16* %ptr2 acquire, align 2
%2 = add i16 %0, %1
store atomic i16 %2, i16* %ptr3 release, align 2
ret i16 %2
}
[Sparc] Handle atomic loads/stores in sparc backend. llvm-svn: 198286
2014-01-02 06:11:54 +08:00
; CHECK-LABEL: test_atomic_i32
; CHECK: ld [%o0]
; CHECK: membar
; CHECK: ld [%o1]
; CHECK: membar
; CHECK: membar
; CHECK: st {{.+}}, [%o2]
define i32 @test_atomic_i32(i32* %ptr1, i32* %ptr2, i32* %ptr3) {
entry:
[SPARC] Fix 8 and 16-bit atomic load and store. They were accidentally using the 32-bit load/store instruction for 8/16-bit operations, due to incorrect patterns (8/16-bit cmpxchg and atomicrmw will be fixed in subsequent changes) llvm-svn: 270486
2016-05-24 04:33:00 +08:00
%0 = load atomic i32, i32* %ptr1 acquire, align 4
%1 = load atomic i32, i32* %ptr2 acquire, align 4
[Sparc] Handle atomic loads/stores in sparc backend. llvm-svn: 198286
2014-01-02 06:11:54 +08:00
%2 = add i32 %0, %1
[SPARC] Fix 8 and 16-bit atomic load and store. They were accidentally using the 32-bit load/store instruction for 8/16-bit operations, due to incorrect patterns (8/16-bit cmpxchg and atomicrmw will be fixed in subsequent changes) llvm-svn: 270486
2016-05-24 04:33:00 +08:00
store atomic i32 %2, i32* %ptr3 release, align 4
[Sparc] Handle atomic loads/stores in sparc backend. llvm-svn: 198286
2014-01-02 06:11:54 +08:00
ret i32 %2
}
Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass. Many CPUs only have the ability to do a 4-byte cmpxchg (or ll/sc), not 1 or 2-byte. For those, you need to mask and shift the 1 or 2 byte values appropriately to use the 4-byte instruction. This change adds support for cmpxchg-based instruction sets (only SPARC, in LLVM). The support can be extended for LL/SC-based PPC and MIPS in the future, supplanting the ISel expansions those architectures currently use. Tests added for the IR transform and SPARCv9. Differential Revision: http://reviews.llvm.org/D21029 llvm-svn: 273025
2016-06-18 02:11:48 +08:00
;; TODO: the "move %icc" and related instructions are totally
;; redundant here. There's something weird happening in optimization
;; of the success value of cmpxchg.
; CHECK-LABEL: test_cmpxchg_i8
; CHECK: and %o1, -4, %o2
; CHECK: mov 3, %o3
; CHECK: andn %o3, %o1, %o1
; CHECK: sll %o1, 3, %o1
; CHECK: mov 255, %o3
; CHECK: sll %o3, %o1, %o5
; CHECK: xor %o5, -1, %o3
; CHECK: mov 123, %o4
; CHECK: ld [%o2], %g2
; CHECK: sll %o4, %o1, %o4
; CHECK: and %o0, 255, %o0
; CHECK: sll %o0, %o1, %o0
; CHECK: andn %g2, %o5, %g2
[Sparc] Use synthetic instruction clr to zero register instead of sethi Using `clr reg`/`mov %g0, reg`/`or %g0, %g0, reg` to zero a register looks much better than `sethi 0, reg`. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45810 llvm-svn: 330396
2018-04-20 15:47:12 +08:00
; CHECK: mov %g0, %o5
Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass. Many CPUs only have the ability to do a 4-byte cmpxchg (or ll/sc), not 1 or 2-byte. For those, you need to mask and shift the 1 or 2 byte values appropriately to use the 4-byte instruction. This change adds support for cmpxchg-based instruction sets (only SPARC, in LLVM). The support can be extended for LL/SC-based PPC and MIPS in the future, supplanting the ISel expansions those architectures currently use. Tests added for the IR transform and SPARCv9. Differential Revision: http://reviews.llvm.org/D21029 llvm-svn: 273025
2016-06-18 02:11:48 +08:00
; CHECK: [[LABEL1:\.L.*]]:
; CHECK: or %g2, %o4, %g3
; CHECK: or %g2, %o0, %g4
; CHECK: cas [%o2], %g4, %g3
; CHECK: cmp %g3, %g4
; CHECK: mov %o5, %g4
; CHECK: move %icc, 1, %g4
; CHECK: cmp %g4, 0
; CHECK: bne [[LABEL2:\.L.*]]
; CHECK: nop
; CHECK: and %g3, %o3, %g4
; CHECK: cmp %g2, %g4
; CHECK: bne [[LABEL1]]
; CHECK: mov %g4, %g2
; CHECK: [[LABEL2]]:
; CHECK: retl
; CHECK: srl %g3, %o1, %o0
define i8 @test_cmpxchg_i8(i8 %a, i8* %ptr) {
entry:
%pair = cmpxchg i8* %ptr, i8 %a, i8 123 monotonic monotonic
%b = extractvalue { i8, i1 } %pair, 0
ret i8 %b
}
; CHECK-LABEL: test_cmpxchg_i16
; CHECK: and %o1, -4, %o2
; CHECK: and %o1, 3, %o1
; CHECK: xor %o1, 2, %o1
; CHECK: sll %o1, 3, %o1
; CHECK: sethi 63, %o3
; CHECK: or %o3, 1023, %o4
; CHECK: sll %o4, %o1, %o5
; CHECK: xor %o5, -1, %o3
; CHECK: and %o0, %o4, %o4
; CHECK: ld [%o2], %g2
; CHECK: mov 123, %o0
; CHECK: sll %o0, %o1, %o0
; CHECK: sll %o4, %o1, %o4
; CHECK: andn %g2, %o5, %g2
[Sparc] Use synthetic instruction clr to zero register instead of sethi Using `clr reg`/`mov %g0, reg`/`or %g0, %g0, reg` to zero a register looks much better than `sethi 0, reg`. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45810 llvm-svn: 330396
2018-04-20 15:47:12 +08:00
; CHECK: mov %g0, %o5
Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass. Many CPUs only have the ability to do a 4-byte cmpxchg (or ll/sc), not 1 or 2-byte. For those, you need to mask and shift the 1 or 2 byte values appropriately to use the 4-byte instruction. This change adds support for cmpxchg-based instruction sets (only SPARC, in LLVM). The support can be extended for LL/SC-based PPC and MIPS in the future, supplanting the ISel expansions those architectures currently use. Tests added for the IR transform and SPARCv9. Differential Revision: http://reviews.llvm.org/D21029 llvm-svn: 273025
2016-06-18 02:11:48 +08:00
; CHECK: [[LABEL1:\.L.*]]:
; CHECK: or %g2, %o0, %g3
; CHECK: or %g2, %o4, %g4
; CHECK: cas [%o2], %g4, %g3
; CHECK: cmp %g3, %g4
; CHECK: mov %o5, %g4
; CHECK: move %icc, 1, %g4
; CHECK: cmp %g4, 0
; CHECK: bne [[LABEL2:\.L.*]]
; CHECK: nop
; CHECK: and %g3, %o3, %g4
; CHECK: cmp %g2, %g4
; CHECK: bne [[LABEL1]]
; CHECK: mov %g4, %g2
; CHECK: [[LABEL2]]:
; CHECK: retl
; CHECK: srl %g3, %o1, %o0
define i16 @test_cmpxchg_i16(i16 %a, i16* %ptr) {
entry:
%pair = cmpxchg i16* %ptr, i16 %a, i16 123 monotonic monotonic
%b = extractvalue { i16, i1 } %pair, 0
ret i16 %b
}
[Sparc] Handle atomic loads/stores in sparc backend. llvm-svn: 198286
2014-01-02 06:11:54 +08:00
; CHECK-LABEL: test_cmpxchg_i32
TableGen: fix operand counting for aliases TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
2014-05-16 17:42:04 +08:00
; CHECK: mov 123, [[R:%[gilo][0-7]]]
[Sparc] Handle atomic loads/stores in sparc backend. llvm-svn: 198286
2014-01-02 06:11:54 +08:00
; CHECK: cas [%o1], %o0, [[R]]
define i32 @test_cmpxchg_i32(i32 %a, i32* %ptr) {
entry:
IR: add "cmpxchg weak" variant to support permitted failure. This commit adds a weak variant of the cmpxchg operation, as described in C++11. A cmpxchg instruction with this modifier is permitted to fail to store, even if the comparison indicated it should. As a result, cmpxchg instructions must return a flag indicating success in addition to their original iN value loaded. Thus, for uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The second flag is 1 when the store succeeded. At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been added as the natural representation for the new cmpxchg instructions. It is a strong cmpxchg. By default this gets Expanded to the existing ATOMIC_CMP_SWAP during Legalization, so existing backends should see no change in behaviour. If they wish to deal with the enhanced node instead, they can call setOperationAction on it. Beware: as a node with 2 results, it cannot be selected from TableGen. Currently, no use is made of the extra information provided in this patch. Test updates are almost entirely adapting the input IR to the new scheme. Summary for out of tree users: ------------------------------ + Legacy Bitcode files are upgraded during read. + Legacy assembly IR files will be invalid. + Front-ends must adapt to different type for "cmpxchg". + Backends should be unaffected by default. llvm-svn: 210903
2014-06-13 22:24:07 +08:00
%pair = cmpxchg i32* %ptr, i32 %a, i32 123 monotonic monotonic
%b = extractvalue { i32, i1 } %pair, 0
[Sparc] Handle atomic loads/stores in sparc backend. llvm-svn: 198286
2014-01-02 06:11:54 +08:00
ret i32 %b
}
Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass. Many CPUs only have the ability to do a 4-byte cmpxchg (or ll/sc), not 1 or 2-byte. For those, you need to mask and shift the 1 or 2 byte values appropriately to use the 4-byte instruction. This change adds support for cmpxchg-based instruction sets (only SPARC, in LLVM). The support can be extended for LL/SC-based PPC and MIPS in the future, supplanting the ISel expansions those architectures currently use. Tests added for the IR transform and SPARCv9. Differential Revision: http://reviews.llvm.org/D21029 llvm-svn: 273025
2016-06-18 02:11:48 +08:00
; CHECK-LABEL: test_swap_i8
; CHECK: mov 42, [[R:%[gilo][0-7]]]
; CHECK: cas
define i8 @test_swap_i8(i8 %a, i8* %ptr) {
entry:
%b = atomicrmw xchg i8* %ptr, i8 42 monotonic
ret i8 %b
}
; CHECK-LABEL: test_swap_i16
; CHECK: mov 42, [[R:%[gilo][0-7]]]
; CHECK: cas
define i16 @test_swap_i16(i16 %a, i16* %ptr) {
entry:
%b = atomicrmw xchg i16* %ptr, i16 42 monotonic
ret i16 %b
}
[Sparc] Handle atomic loads/stores in sparc backend. llvm-svn: 198286
2014-01-02 06:11:54 +08:00
; CHECK-LABEL: test_swap_i32
TableGen: fix operand counting for aliases TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
2014-05-16 17:42:04 +08:00
; CHECK: mov 42, [[R:%[gilo][0-7]]]
[Sparc] Handle atomic loads/stores in sparc backend. llvm-svn: 198286
2014-01-02 06:11:54 +08:00
; CHECK: swap [%o1], [[R]]
define i32 @test_swap_i32(i32 %a, i32* %ptr) {
entry:
%b = atomicrmw xchg i32* %ptr, i32 42 monotonic
ret i32 %b
}
Implement atomicrmw operations in 32 and 64 bits for SPARCv9. These all use the compare-and-swap CASA/CASXA instructions. llvm-svn: 199975
2014-01-24 14:23:31 +08:00
Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass. Many CPUs only have the ability to do a 4-byte cmpxchg (or ll/sc), not 1 or 2-byte. For those, you need to mask and shift the 1 or 2 byte values appropriately to use the 4-byte instruction. This change adds support for cmpxchg-based instruction sets (only SPARC, in LLVM). The support can be extended for LL/SC-based PPC and MIPS in the future, supplanting the ISel expansions those architectures currently use. Tests added for the IR transform and SPARCv9. Differential Revision: http://reviews.llvm.org/D21029 llvm-svn: 273025
2016-06-18 02:11:48 +08:00
; CHECK-LABEL: test_load_sub_i8
; CHECK: membar
; CHECK: .L{{.*}}:
; CHECK: sub
; CHECK: cas [{{%[gilo][0-7]}}]
; CHECK: membar
define zeroext i8 @test_load_sub_i8(i8* %p, i8 zeroext %v) {
entry:
%0 = atomicrmw sub i8* %p, i8 %v seq_cst
ret i8 %0
}
; CHECK-LABEL: test_load_sub_i16
; CHECK: membar
; CHECK: .L{{.*}}:
; CHECK: sub
; CHECK: cas [{{%[gilo][0-7]}}]
; CHECK: membar
define zeroext i16 @test_load_sub_i16(i16* %p, i16 zeroext %v) {
entry:
%0 = atomicrmw sub i16* %p, i16 %v seq_cst
ret i16 %0
}
; CHECK-LABEL: test_load_add_i32
Implement atomicrmw operations in 32 and 64 bits for SPARCv9. These all use the compare-and-swap CASA/CASXA instructions. llvm-svn: 199975
2014-01-24 14:23:31 +08:00
; CHECK: membar
[Sparc] Use synthetic instruction clr to zero register instead of sethi Using `clr reg`/`mov %g0, reg`/`or %g0, %g0, reg` to zero a register looks much better than `sethi 0, reg`. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45810 llvm-svn: 330396
2018-04-20 15:47:12 +08:00
; CHECK: mov %g0
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" Re-enable commit r323991 now that r325931 has been committed to make MachineOperand::isRenamable() check more conservative w.r.t. code changes and opt-in on a per-target basis. llvm-svn: 326208
2018-02-28 00:59:10 +08:00
; CHECK: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
; CHECK: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
; CHECK: cas [%o0], [[V]], [[V2]]
Implement atomicrmw operations in 32 and 64 bits for SPARCv9. These all use the compare-and-swap CASA/CASXA instructions. llvm-svn: 199975
2014-01-24 14:23:31 +08:00
; CHECK: membar
Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass. Many CPUs only have the ability to do a 4-byte cmpxchg (or ll/sc), not 1 or 2-byte. For those, you need to mask and shift the 1 or 2 byte values appropriately to use the 4-byte instruction. This change adds support for cmpxchg-based instruction sets (only SPARC, in LLVM). The support can be extended for LL/SC-based PPC and MIPS in the future, supplanting the ISel expansions those architectures currently use. Tests added for the IR transform and SPARCv9. Differential Revision: http://reviews.llvm.org/D21029 llvm-svn: 273025
2016-06-18 02:11:48 +08:00
define zeroext i32 @test_load_add_i32(i32* %p, i32 zeroext %v) {
Implement atomicrmw operations in 32 and 64 bits for SPARCv9. These all use the compare-and-swap CASA/CASXA instructions. llvm-svn: 199975
2014-01-24 14:23:31 +08:00
entry:
%0 = atomicrmw add i32* %p, i32 %v seq_cst
ret i32 %0
}
; CHECK-LABEL: test_load_xor_32
; CHECK: membar
; CHECK: xor
; CHECK: cas [%o0]
; CHECK: membar
define zeroext i32 @test_load_xor_32(i32* %p, i32 zeroext %v) {
entry:
%0 = atomicrmw xor i32* %p, i32 %v seq_cst
ret i32 %0
}
; CHECK-LABEL: test_load_and_32
; CHECK: membar
; CHECK: and
; CHECK-NOT: xor
; CHECK: cas [%o0]
; CHECK: membar
define zeroext i32 @test_load_and_32(i32* %p, i32 zeroext %v) {
entry:
%0 = atomicrmw and i32* %p, i32 %v seq_cst
ret i32 %0
}
; CHECK-LABEL: test_load_nand_32
; CHECK: membar
; CHECK: and
; CHECK: xor
; CHECK: cas [%o0]
; CHECK: membar
define zeroext i32 @test_load_nand_32(i32* %p, i32 zeroext %v) {
entry:
%0 = atomicrmw nand i32* %p, i32 %v seq_cst
ret i32 %0
}
; CHECK-LABEL: test_load_umin_32
; CHECK: membar
; CHECK: cmp
; CHECK: movleu %icc
; CHECK: cas [%o0]
; CHECK: membar
define zeroext i32 @test_load_umin_32(i32* %p, i32 zeroext %v) {
entry:
%0 = atomicrmw umin i32* %p, i32 %v seq_cst
ret i32 %0
}