llvm-project/llvm/test/MC/X86/intel-syntax-32.s

// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel %s | FileCheck %s

// CHECK: leaw	(%bp,%si), %ax
lea ax, [bp+si]
// CHECK: leaw	(%bp,%si), %ax
lea ax, [si+bp]
[X86] Don't accept (%si,%bp) 16-bit address expressions. The second register is the index register and should only be %si or %di if used with a base register. And in that case the base register should be %bp or %bx. This makes us compatible with gas. We do still need to support both orders with Intel syntax which uses [bp+si] and [si+bp] llvm-svn: 335384 2018-06-23 04:20:38 +08:00			`// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel %s \| FileCheck %s`

			`// CHECK: leaw (%bp,%si), %ax`
			`lea ax, [bp+si]`
			`// CHECK: leaw (%bp,%si), %ax`
			`lea ax, [si+bp]`