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llvm-project/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll

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Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 llvm-svn: 104060
2010-05-19 05:31:17 +08:00
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB
; rdar://7998649
%struct.foo = type { i64, i64 }
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define zeroext i8 @t(%struct.foo* %this) noreturn optsize {
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 llvm-svn: 104060
2010-05-19 05:31:17 +08:00
entry:
; ARM: t:
don't test for codegen of 'store undef' llvm-svn: 129184
2011-04-09 10:31:26 +08:00
; ARM: str r2, [r1], r0
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 llvm-svn: 104060
2010-05-19 05:31:17 +08:00
; THUMB: t:
; THUMB-NOT: str r0, [r1], r0
Tighten physical register invariants: Allocatable physical registers can only be live in to a block if it is the function entry point or a landing pad. llvm-svn: 150494
2012-02-15 02:51:53 +08:00
; THUMB: str r1, [r0]
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 llvm-svn: 104060
2010-05-19 05:31:17 +08:00
%0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1]
don't test for codegen of 'store undef' llvm-svn: 129184
2011-04-09 10:31:26 +08:00
store i32 0, i32* inttoptr (i32 8 to i32*), align 8
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 llvm-svn: 104060
2010-05-19 05:31:17 +08:00
br i1 undef, label %bb.nph96, label %bb3
bb3: ; preds = %entry
%1 = load i64* %0, align 4 ; <i64> [#uses=0]
unreachable
bb.nph96: ; preds = %entry
unreachable
}