2012-02-18 20:03:15 +08:00
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//===-- PPCFrameLowering.h - Define frame lowering for PowerPC --*- C++ -*-===//
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2005-04-22 07:30:14 +08:00
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//
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2004-08-15 06:16:36 +08:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 07:30:14 +08:00
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//
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2004-08-15 06:16:36 +08:00
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//===----------------------------------------------------------------------===//
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//
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//
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2005-10-16 13:39:50 +08:00
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//===----------------------------------------------------------------------===//
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2004-08-15 06:16:36 +08:00
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2014-08-14 00:26:38 +08:00
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCFRAMELOWERING_H
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#define LLVM_LIB_TARGET_POWERPC_PPCFRAMELOWERING_H
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2004-08-15 06:16:36 +08:00
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2005-10-15 07:51:18 +08:00
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#include "PPC.h"
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2012-12-04 15:12:27 +08:00
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#include "llvm/ADT/STLExtras.h"
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2011-01-10 20:39:04 +08:00
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#include "llvm/Target/TargetFrameLowering.h"
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2004-08-15 06:16:36 +08:00
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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2014-06-13 04:54:11 +08:00
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class PPCSubtarget;
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2004-08-15 06:16:36 +08:00
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2011-01-10 20:39:04 +08:00
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class PPCFrameLowering: public TargetFrameLowering {
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2010-11-15 08:06:54 +08:00
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const PPCSubtarget &Subtarget;
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2015-02-13 08:39:27 +08:00
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const unsigned ReturnSaveOffset;
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2015-02-13 08:39:36 +08:00
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const unsigned TOCSaveOffset;
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2015-02-13 08:39:38 +08:00
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const unsigned FramePointerSaveOffset;
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2015-02-14 06:22:57 +08:00
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const unsigned LinkageSize;
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2015-02-14 06:48:53 +08:00
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const unsigned BasePointerSaveOffset;
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2005-04-22 07:30:14 +08:00
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2015-11-17 04:22:15 +08:00
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/**
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2016-02-21 02:16:25 +08:00
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* \brief Find register[s] that can be used in function prologue and epilogue
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2015-11-17 04:22:15 +08:00
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*
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2016-02-21 02:16:25 +08:00
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* Find register[s] that can be use as scratch register[s] in function
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2015-11-17 04:22:15 +08:00
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* prologue and epilogue to save various registers (Link Register, Base
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2016-02-21 02:16:25 +08:00
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* Pointer, etc.). Prefer R0/R12, if available. Otherwise choose whatever
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* register[s] are available.
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2015-11-17 04:22:15 +08:00
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*
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2016-02-21 02:16:25 +08:00
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* This method will return true if it is able to find enough unique scratch
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* registers (1 or 2 depending on the requirement). If it is unable to find
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* enough available registers in the block, it will return false and set
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* any passed output parameter that corresponds to a required unique register
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* to PPC::NoRegister.
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2015-11-17 04:22:15 +08:00
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*
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* \param[in] MBB The machine basic block to find an available register for
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* \param[in] UseAtEnd Specify whether the scratch register will be used at
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* the end of the basic block (i.e., will the scratch
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* register kill a register defined in the basic block)
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2016-02-21 02:16:25 +08:00
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* \param[in] TwoUniqueRegsRequired Specify whether this basic block will
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* require two unique scratch registers.
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* \param[out] SR1 The scratch register to use
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* \param[out] SR2 The second scratch register. If this pointer is not null
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* the function will attempt to set it to an available
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* register regardless of whether there is a hard requirement
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* for two unique scratch registers.
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* \return true if the required number of registers was found.
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* false if the required number of scratch register weren't available.
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* If either output parameter refers to a required scratch register
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* that isn't available, it will be set to an invalid value.
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2015-11-17 04:22:15 +08:00
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*/
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bool findScratchRegister(MachineBasicBlock *MBB,
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bool UseAtEnd,
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2016-02-21 02:16:25 +08:00
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bool TwoUniqueRegsRequired = false,
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unsigned *SR1 = nullptr,
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unsigned *SR2 = nullptr) const;
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bool twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const;
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2015-11-17 04:22:15 +08:00
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[PPC64] Bug fix: when enabling sibling-call-opt and shrink-wrapping, the tail call branch instruction might disappear
Bug Pattern:
# BB#0: # %entry
cmpldi 3, 0
beq- 0, .LBB0_2
# BB#1: # %exit
lwz 4, 0(3)
#TC_RETURNd8 LVComputationKind 0
.LBB0_2: # %cond.false
mflr 0
std 0, 16(1)
stdu 1, -96(1)
.Ltmp0:
.cfi_def_cfa_offset 96
.Ltmp1:
.cfi_offset lr, 16
bl __assert_fail
nop
The branch instruction for tail call return is not generated, because the
shrink-wrapping pass choosing a new Restore Point: %cond.false, so %exit
block is not sent to emitEpilogue, that's why the branch is not generated.
Thanks Kit's opinions!
Reviewers: nemanjai hfinkel tjablin kbarton
http://reviews.llvm.org/D17606
llvm-svn: 265112
2016-04-01 14:44:32 +08:00
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/**
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* \brief Create branch instruction for PPC::TCRETURN* (tail call return)
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*
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* \param[in] MBB that is terminated by PPC::TCRETURN*
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*/
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void createTailCallBranchInstr(MachineBasicBlock &MBB) const;
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2004-08-15 06:16:36 +08:00
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public:
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2014-06-13 04:54:11 +08:00
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PPCFrameLowering(const PPCSubtarget &STI);
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2004-08-15 06:16:36 +08:00
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2013-03-15 13:06:04 +08:00
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unsigned determineFrameLayout(MachineFunction &MF,
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bool UpdateMF = true,
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bool UseEstimate = false) const;
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2010-11-15 08:06:54 +08:00
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function.
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[ShrinkWrap] Add (a simplified version) of shrink-wrapping.
This patch introduces a new pass that computes the safe point to insert the
prologue and epilogue of the function.
The interest is to find safe points that are cheaper than the entry and exits
blocks.
As an example and to avoid regressions to be introduce, this patch also
implements the required bits to enable the shrink-wrapping pass for AArch64.
** Context **
Currently we insert the prologue and epilogue of the method/function in the
entry and exits blocks. Although this is correct, we can do a better job when
those are not immediately required and insert them at less frequently executed
places.
The job of the shrink-wrapping pass is to identify such places.
** Motivating example **
Let us consider the following function that perform a call only in one branch of
a if:
define i32 @f(i32 %a, i32 %b) {
%tmp = alloca i32, align 4
%tmp2 = icmp slt i32 %a, %b
br i1 %tmp2, label %true, label %false
true:
store i32 %a, i32* %tmp, align 4
%tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
br label %false
false:
%tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
ret i32 %tmp.0
}
On AArch64 this code generates (removing the cfi directives to ease
readabilities):
_f: ; @f
; BB#0:
stp x29, x30, [sp, #-16]!
mov x29, sp
sub sp, sp, #16 ; =16
cmp w0, w1
b.ge LBB0_2
; BB#1: ; %true
stur w0, [x29, #-4]
sub x1, x29, #4 ; =4
mov w0, wzr
bl _doSomething
LBB0_2: ; %false
mov sp, x29
ldp x29, x30, [sp], #16
ret
With shrink-wrapping we could generate:
_f: ; @f
; BB#0:
cmp w0, w1
b.ge LBB0_2
; BB#1: ; %true
stp x29, x30, [sp, #-16]!
mov x29, sp
sub sp, sp, #16 ; =16
stur w0, [x29, #-4]
sub x1, x29, #4 ; =4
mov w0, wzr
bl _doSomething
add sp, x29, #16 ; =16
ldp x29, x30, [sp], #16
LBB0_2: ; %false
ret
Therefore, we would pay the overhead of setting up/destroying the frame only if
we actually do the call.
** Proposed Solution **
This patch introduces a new machine pass that perform the shrink-wrapping
analysis (See the comments at the beginning of ShrinkWrap.cpp for more details).
It then stores the safe save and restore point into the MachineFrameInfo
attached to the MachineFunction.
This information is then used by the PrologEpilogInserter (PEI) to place the
related code at the right place. This pass runs right before the PEI.
Unlike the original paper of Chow from PLDI’88, this implementation of
shrink-wrapping does not use expensive data-flow analysis and does not need hack
to properly avoid frequently executed point. Instead, it relies on dominance and
loop properties.
The pass is off by default and each target can opt-in by setting the
EnableShrinkWrap boolean to true in their derived class of TargetPassConfig.
This setting can also be overwritten on the command line by using
-enable-shrink-wrap.
Before you try out the pass for your target, make sure you properly fix your
emitProlog/emitEpilog/adjustForXXX method to cope with basic blocks that are not
necessarily the entry block.
** Design Decisions **
1. ShrinkWrap is its own pass right now. It could frankly be merged into PEI but
for debugging and clarity I thought it was best to have its own file.
2. Right now, we only support one save point and one restore point. At some
point we can expand this to several save point and restore point, the impacted
component would then be:
- The pass itself: New algorithm needed.
- MachineFrameInfo: Hold a list or set of Save/Restore point instead of one
pointer.
- PEI: Should loop over the save point and restore point.
Anyhow, at least for this first iteration, I do not believe this is interesting
to support the complex cases. We should revisit that when we motivating
examples.
Differential Revision: http://reviews.llvm.org/D9210
<rdar://problem/3201744>
llvm-svn: 236507
2015-05-06 01:38:16 +08:00
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void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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2014-04-29 15:57:37 +08:00
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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2010-11-15 08:06:54 +08:00
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2014-04-29 15:57:37 +08:00
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bool hasFP(const MachineFunction &MF) const override;
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2010-12-19 03:53:14 +08:00
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bool needsFP(const MachineFunction &MF) const;
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2013-03-22 03:03:19 +08:00
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void replaceFPWithRealFP(MachineFunction &MF) const;
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2010-11-19 05:19:35 +08:00
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2015-07-15 01:17:13 +08:00
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS = nullptr) const override;
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2013-03-15 04:33:40 +08:00
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void processFunctionBeforeFrameFinalized(MachineFunction &MF,
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2014-04-29 15:57:37 +08:00
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RegScavenger *RS = nullptr) const override;
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2013-03-15 13:06:04 +08:00
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void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
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2010-11-28 07:05:25 +08:00
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2012-09-12 22:47:47 +08:00
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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2014-04-29 15:57:37 +08:00
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const TargetRegisterInfo *TRI) const override;
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2012-09-12 22:47:47 +08:00
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2016-04-01 02:33:38 +08:00
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const override;
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2013-02-22 04:05:00 +08:00
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2012-09-12 22:47:47 +08:00
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bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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2014-04-29 15:57:37 +08:00
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MachineBasicBlock::iterator MI,
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2017-08-11 00:17:32 +08:00
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std::vector<CalleeSavedInfo> &CSI,
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2014-04-29 15:57:37 +08:00
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const TargetRegisterInfo *TRI) const override;
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2012-09-12 22:47:47 +08:00
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2010-11-15 08:06:54 +08:00
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/// targetHandlesStackFrameRounding - Returns true if the target is
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/// responsible for rounding up the stack frame (probably at emitPrologue
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/// time).
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2014-04-29 15:57:37 +08:00
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bool targetHandlesStackFrameRounding() const override { return true; }
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2010-11-15 08:06:54 +08:00
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2006-12-07 01:42:06 +08:00
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/// getReturnSaveOffset - Return the previous frame offset to save the
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/// return address.
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2015-02-13 08:39:27 +08:00
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unsigned getReturnSaveOffset() const { return ReturnSaveOffset; }
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2006-12-07 01:42:06 +08:00
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[PowerPC] Simplify and improve loading into TOC register
During an indirect function call sequence on the 64-bit SVR4 ABI,
generate code must load and then restore the TOC register.
This does not use a regular LOAD instruction since the TOC
register r2 is marked as reserved. Instead, the are two
special instruction patterns:
let RST = 2, DS = 2 in
def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
"ld 2, 8($reg)", IIC_LdStLD,
[(PPCload_toc i64:$reg)]>, isPPC64;
let RST = 2, DS = 10, RA = 1 in
def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
"ld 2, 40(1)", IIC_LdStLD,
[(PPCtoc_restore)]>, isPPC64;
Note that these not only restrict the destination of the
load to r2, but they also restrict the *source* of the
load to particular address combinations. The latter is
a problem when we want to support the ELFv2 ABI, since
there the TOC save slot is no longer at 40(1).
This patch replaces those two instructions with a single
instruction pattern that only hard-codes r2 as destination,
but supports generic addresses as source. This will allow
supporting the ELFv2 ABI, and also helps generate more
efficient code for calls to absolute addresses (allowing
simplification of the ppc64-calls.ll test case).
llvm-svn: 211193
2014-06-19 01:52:49 +08:00
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/// getTOCSaveOffset - Return the previous frame offset to save the
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/// TOC register -- 64-bit SVR4 ABI only.
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2015-02-13 08:39:36 +08:00
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unsigned getTOCSaveOffset() const { return TOCSaveOffset; }
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[PowerPC] Simplify and improve loading into TOC register
During an indirect function call sequence on the 64-bit SVR4 ABI,
generate code must load and then restore the TOC register.
This does not use a regular LOAD instruction since the TOC
register r2 is marked as reserved. Instead, the are two
special instruction patterns:
let RST = 2, DS = 2 in
def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
"ld 2, 8($reg)", IIC_LdStLD,
[(PPCload_toc i64:$reg)]>, isPPC64;
let RST = 2, DS = 10, RA = 1 in
def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
"ld 2, 40(1)", IIC_LdStLD,
[(PPCtoc_restore)]>, isPPC64;
Note that these not only restrict the destination of the
load to r2, but they also restrict the *source* of the
load to particular address combinations. The latter is
a problem when we want to support the ELFv2 ABI, since
there the TOC save slot is no longer at 40(1).
This patch replaces those two instructions with a single
instruction pattern that only hard-codes r2 as destination,
but supports generic addresses as source. This will allow
supporting the ELFv2 ABI, and also helps generate more
efficient code for calls to absolute addresses (allowing
simplification of the ppc64-calls.ll test case).
llvm-svn: 211193
2014-06-19 01:52:49 +08:00
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2006-11-17 06:43:37 +08:00
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/// getFramePointerSaveOffset - Return the previous frame offset to save the
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/// frame pointer.
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2015-02-13 08:39:38 +08:00
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unsigned getFramePointerSaveOffset() const { return FramePointerSaveOffset; }
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2010-11-15 08:06:05 +08:00
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2013-07-17 08:45:52 +08:00
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/// getBasePointerSaveOffset - Return the previous frame offset to save the
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/// base pointer.
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2015-02-14 06:48:53 +08:00
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unsigned getBasePointerSaveOffset() const { return BasePointerSaveOffset; }
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2013-07-17 08:45:52 +08:00
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2006-11-17 06:43:37 +08:00
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/// getLinkageSize - Return the size of the PowerPC ABI linkage area.
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///
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2015-02-14 06:22:57 +08:00
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unsigned getLinkageSize() const { return LinkageSize; }
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2006-11-17 06:43:37 +08:00
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2009-09-28 01:58:47 +08:00
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const SpillSlot *
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2014-06-13 04:54:11 +08:00
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getCalleeSavedSpillSlots(unsigned &NumEntries) const override;
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2015-09-10 09:55:44 +08:00
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bool enableShrinkWrapping(const MachineFunction &MF) const override;
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2015-11-17 04:22:15 +08:00
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/// Methods used by shrink wrapping to determine if MBB can be used for the
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/// function prologue/epilogue.
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bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
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bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override;
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2004-08-15 06:16:36 +08:00
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};
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2015-06-23 17:49:53 +08:00
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} // End llvm namespace
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2004-08-15 06:16:36 +08:00
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#endif
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