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llvm-project/llvm/lib/Target/PowerPC/PPC.td

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Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td llvm-svn: 23738
2005-10-15 07:37:35 +08:00
//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This is the top level entry point for the PowerPC target.
//
//===----------------------------------------------------------------------===//
// Get the target-independent interfaces which we are implementing.
//
include "../Target.td"
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
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//===----------------------------------------------------------------------===//
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
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// PowerPC Subtarget features.
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
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//
Rename some subtarget features. A CPU now can *have* 64-bit instructions, can in 32-bit mode we can choose to optionally *use* 64-bit registers. llvm-svn: 28824
2006-06-17 01:34:12 +08:00
def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
improve -help output llvm-svn: 23892
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"Enable 64-bit instructions">;
Rename some subtarget features. A CPU now can *have* 64-bit instructions, can in 32-bit mode we can choose to optionally *use* 64-bit registers. llvm-svn: 28824
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def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
"Enable 64-bit registers usage for ppc32 [beta]">;
Subtarget feature can now set any variable to any value llvm-svn: 25678
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def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
improve -help output llvm-svn: 23892
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"Enable Altivec instructions">;
Subtarget feature can now set any variable to any value llvm-svn: 25678
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def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
improve -help output llvm-svn: 23892
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"Enable GPUL instructions">;
Subtarget feature can now set any variable to any value llvm-svn: 25678
2006-01-27 16:09:42 +08:00
def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
improve -help output llvm-svn: 23892
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"Enable the fsqrt instruction">;
Add a subtarget feature for the stfiwx instruction. I know the G5 has it, but I don't know what other PPC impls do. If someone could update the proc table, I would appreciate it :) llvm-svn: 26421
2006-02-28 15:08:22 +08:00
def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
"Enable the stfiwx instruction">;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
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//===----------------------------------------------------------------------===//
rearrange things a bit so that instructions can use subtarget features in the future. llvm-svn: 23902
2005-10-24 06:08:13 +08:00
// Register File Description
//===----------------------------------------------------------------------===//
include "PPCRegisterInfo.td"
include "PPCSchedule.td"
include "PPCInstrInfo.td"
//===----------------------------------------------------------------------===//
// PowerPC processors supported.
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
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//
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
def : Processor<"generic", G3Itineraries, []>;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
def : Processor<"601", G3Itineraries, []>;
def : Processor<"602", G3Itineraries, []>;
def : Processor<"603", G3Itineraries, []>;
Plugin new subtarget backend into the build. llvm-svn: 23870
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def : Processor<"603e", G3Itineraries, []>;
def : Processor<"603ev", G3Itineraries, []>;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
def : Processor<"604", G3Itineraries, []>;
Plugin new subtarget backend into the build. llvm-svn: 23870
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def : Processor<"604e", G3Itineraries, []>;
def : Processor<"620", G3Itineraries, []>;
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
def : Processor<"g3", G3Itineraries, []>;
Plugin new subtarget backend into the build. llvm-svn: 23870
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def : Processor<"7400", G4Itineraries, [FeatureAltivec]>;
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
Plugin new subtarget backend into the build. llvm-svn: 23870
2005-10-22 03:05:19 +08:00
def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
def : Processor<"750", G3Itineraries, []>;
def : Processor<"970", G5Itineraries,
Add a subtarget feature for the stfiwx instruction. I know the G5 has it, but I don't know what other PPC impls do. If someone could update the proc table, I would appreciate it :) llvm-svn: 26421
2006-02-28 15:08:22 +08:00
[FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
Feature64Bit /*, Feature64BitRegs */]>;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
def : Processor<"g5", G5Itineraries,
Add a subtarget feature for the stfiwx instruction. I know the G5 has it, but I don't know what other PPC impls do. If someone could update the proc table, I would appreciate it :) llvm-svn: 26421
2006-02-28 15:08:22 +08:00
[FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
Feature64Bit /*, Feature64BitRegs */]>;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
Several big changes: 1. Use flags on the instructions in the .td file to indicate the PPC970 unit type instead of a table in the .cpp file. Much cleaner. 2. Change the hazard recognizer to build d-groups according to the actual algorithm used, not my flawed understanding of it. 3. Model "must be in the first slot" and "must be the only instr in a group" accurately. llvm-svn: 26719
2006-03-12 17:13:49 +08:00
def PPCInstrInfo : InstrInfo {
// Define how we want to layout our TargetSpecific information field... This
// should be kept up-to-date with the fields in the PPCInstrInfo.h file.
let TSFlagsFields = ["PPC970_First",
"PPC970_Single",
Mark instructions that are cracked by the PPC970 decoder as such. llvm-svn: 26720
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"PPC970_Cracked",
Several big changes: 1. Use flags on the instructions in the .td file to indicate the PPC970 unit type instead of a table in the .cpp file. Much cleaner. 2. Change the hazard recognizer to build d-groups according to the actual algorithm used, not my flawed understanding of it. 3. Model "must be in the first slot" and "must be the only instr in a group" accurately. llvm-svn: 26719
2006-03-12 17:13:49 +08:00
"PPC970_Unit"];
Mark instructions that are cracked by the PPC970 decoder as such. llvm-svn: 26720
2006-03-13 13:15:10 +08:00
let TSFlagsShifts = [0, 1, 2, 3];
Several big changes: 1. Use flags on the instructions in the .td file to indicate the PPC970 unit type instead of a table in the .cpp file. Much cleaner. 2. Change the hazard recognizer to build d-groups according to the actual algorithm used, not my flawed understanding of it. 3. Model "must be in the first slot" and "must be the only instr in a group" accurately. llvm-svn: 26719
2006-03-12 17:13:49 +08:00
let isLittleEndianEncoding = 1;
}
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td llvm-svn: 23738
2005-10-15 07:37:35 +08:00
def PPC : Target {
Several big changes: 1. Use flags on the instructions in the .td file to indicate the PPC970 unit type instead of a table in the .cpp file. Much cleaner. 2. Change the hazard recognizer to build d-groups according to the actual algorithm used, not my flawed understanding of it. 3. Model "must be in the first slot" and "must be the only instr in a group" accurately. llvm-svn: 26719
2006-03-12 17:13:49 +08:00
// Information about the instructions.
let InstructionSet = PPCInstrInfo;
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td llvm-svn: 23738
2005-10-15 07:37:35 +08:00
}