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llvm-project/llvm/test/CodeGen/ARM/fpconsts.ll

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Use fconsts and fconstd to materialize small fp constants. llvm-svn: 85362
2009-10-28 09:44:26 +08:00
; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define float @t1(float %x) nounwind readnone optsize {
Use fconsts and fconstd to materialize small fp constants. llvm-svn: 85362
2009-10-28 09:44:26 +08:00
entry:
; CHECK: t1:
Convert -enable-sched-cycles and -enable-sched-hazard to -disable flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
2011-01-21 13:51:33 +08:00
; CHECK: vmov.f32 s{{.*}}, #4.000000e+00
Use fconsts and fconstd to materialize small fp constants. llvm-svn: 85362
2009-10-28 09:44:26 +08:00
%0 = fadd float %x, 4.000000e+00
ret float %0
}
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define double @t2(double %x) nounwind readnone optsize {
Use fconsts and fconstd to materialize small fp constants. llvm-svn: 85362
2009-10-28 09:44:26 +08:00
entry:
; CHECK: t2:
Change register allocation order for ARM VFP and NEON registers to put the callee-saved registers at the end of the lists. Also prefer to avoid using the low registers that are in register subclasses required by certain instructions, so that those registers will more likely be available when needed. This change makes a huge improvement in spilling in some cases. Thanks to Jakob for helping me realize the problem. Most of this patch is fixing the testsuite. There are quite a few places where we're checking for specific registers. I changed those to wildcards in places where that doesn't weaken the tests. The spill-q.ll and thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch of live values to force spills on those tests. llvm-svn: 116055
2010-10-08 14:15:13 +08:00
; CHECK: vmov.f64 d{{.*}}, #3.000000e+00
Use fconsts and fconstd to materialize small fp constants. llvm-svn: 85362
2009-10-28 09:44:26 +08:00
%0 = fadd double %x, 3.000000e+00
ret double %0
}
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define double @t3(double %x) nounwind readnone optsize {
Use fconsts and fconstd to materialize small fp constants. llvm-svn: 85362
2009-10-28 09:44:26 +08:00
entry:
; CHECK: t3:
Change register allocation order for ARM VFP and NEON registers to put the callee-saved registers at the end of the lists. Also prefer to avoid using the low registers that are in register subclasses required by certain instructions, so that those registers will more likely be available when needed. This change makes a huge improvement in spilling in some cases. Thanks to Jakob for helping me realize the problem. Most of this patch is fixing the testsuite. There are quite a few places where we're checking for specific registers. I changed those to wildcards in places where that doesn't weaken the tests. The spill-q.ll and thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch of live values to force spills on those tests. llvm-svn: 116055
2010-10-08 14:15:13 +08:00
; CHECK: vmov.f64 d{{.*}}, #-1.300000e+01
Use fconsts and fconstd to materialize small fp constants. llvm-svn: 85362
2009-10-28 09:44:26 +08:00
%0 = fmul double %x, -1.300000e+01
ret double %0
}
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define float @t4(float %x) nounwind readnone optsize {
Use fconsts and fconstd to materialize small fp constants. llvm-svn: 85362
2009-10-28 09:44:26 +08:00
entry:
; CHECK: t4:
Convert -enable-sched-cycles and -enable-sched-hazard to -disable flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
2011-01-21 13:51:33 +08:00
; CHECK: vmov.f32 s{{.*}}, #-2.400000e+01
Use fconsts and fconstd to materialize small fp constants. llvm-svn: 85362
2009-10-28 09:44:26 +08:00
%0 = fmul float %x, -2.400000e+01
ret float %0
}