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llvm-project/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-...

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ARM: Correctly align arguments after a byval struct is passed on the stack llvm-svn: 202985
2014-03-05 23:25:27 +08:00
; RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
%struct4bytes = type { i32 }
%struct8bytes8align = type { i64 }
%struct12bytes = type { i32, i32, i32 }
declare void @useIntPtr(%struct4bytes*)
declare void @useLong(i64)
declare void @usePtr(%struct8bytes8align*)
; a -> r0
; b -> r1..r3
; c -> sp+0..sp+7
define void @foo1(i32 %a, %struct12bytes* byval %b, i64 %c) {
; CHECK-LABEL: foo1
ARM: simplify and extend byval handling The main issue being fixed here is that APCS targets handling a "byval align N" parameter with N > 4 were miscounting what objects were where on the stack, leading to FrameLowering setting the frame pointer incorrectly and clobbering the stack. But byval handling had grown over many years, and had multiple layers of cruft trying to compensate for each other and calculate padding correctly. This only really needs to be done once, in the HandleByVal function. Elsewhere should just do what it's told by that call. I also stripped out unnecessary APCS/AAPCS distinctions (now that Clang emits byvals with the correct C ABI alignment), which simplified HandleByVal. rdar://20095672 llvm-svn: 231959
2015-03-12 02:54:22 +08:00
; CHECK: sub sp, sp, #12
ARM: Correctly align arguments after a byval struct is passed on the stack llvm-svn: 202985
2014-03-05 23:25:27 +08:00
; CHECK: push {r11, lr}
ARM: simplify and extend byval handling The main issue being fixed here is that APCS targets handling a "byval align N" parameter with N > 4 were miscounting what objects were where on the stack, leading to FrameLowering setting the frame pointer incorrectly and clobbering the stack. But byval handling had grown over many years, and had multiple layers of cruft trying to compensate for each other and calculate padding correctly. This only really needs to be done once, in the HandleByVal function. Elsewhere should just do what it's told by that call. I also stripped out unnecessary APCS/AAPCS distinctions (now that Clang emits byvals with the correct C ABI alignment), which simplified HandleByVal. rdar://20095672 llvm-svn: 231959
2015-03-12 02:54:22 +08:00
; CHECK: sub sp, sp, #4
ARM: Correctly align arguments after a byval struct is passed on the stack llvm-svn: 202985
2014-03-05 23:25:27 +08:00
; CHECK: add [[SCRATCH:r[0-9]+]], sp, #12
; CHECK: stm [[SCRATCH]], {r1, r2, r3}
; CHECK: ldr r0, [sp, #24]
; CHECK: ldr r1, [sp, #28]
; CHECK: bl useLong
; CHECK: pop {r11, lr}
ARM: simplify and extend byval handling The main issue being fixed here is that APCS targets handling a "byval align N" parameter with N > 4 were miscounting what objects were where on the stack, leading to FrameLowering setting the frame pointer incorrectly and clobbering the stack. But byval handling had grown over many years, and had multiple layers of cruft trying to compensate for each other and calculate padding correctly. This only really needs to be done once, in the HandleByVal function. Elsewhere should just do what it's told by that call. I also stripped out unnecessary APCS/AAPCS distinctions (now that Clang emits byvals with the correct C ABI alignment), which simplified HandleByVal. rdar://20095672 llvm-svn: 231959
2015-03-12 02:54:22 +08:00
; CHECK: add sp, sp, #12
ARM: Correctly align arguments after a byval struct is passed on the stack llvm-svn: 202985
2014-03-05 23:25:27 +08:00
ARM: enable tail call optimisation on Thumb 2 Tail call optimisation was previously disabled on all targets other than iOS5.0+. This enables the tail call optimisation on all Thumb 2 capable platforms. The test adjustments are to remove the IR hint "tail" to function invocation. The tests were designed assuming that tail call optimisations would not kick in which no longer holds true. llvm-svn: 203575
2014-03-11 23:09:44 +08:00
call void @useLong(i64 %c)
ARM: Correctly align arguments after a byval struct is passed on the stack llvm-svn: 202985
2014-03-05 23:25:27 +08:00
ret void
}
; a -> r0
; b -> r2..r3
define void @foo2(i32 %a, %struct8bytes8align* byval %b) {
; CHECK-LABEL: foo2
; CHECK: sub sp, sp, #8
; CHECK: push {r11, lr}
; CHECK: add r0, sp, #8
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later. Summary: A number of optimizations are inhibited by single-use TokenFactors not being merged into the TokenFactor using it. This makes we consider if we can do the merge immediately. Most tests changes here are due to the change in visitation causing minor reorderings and associated reassociation of paired memory operations. CodeGen tests with non-reordering changes: X86/aligned-variadic.ll -- memory-based add folded into stored leaq value. X86/constant-combiners.ll -- Optimizes out overlap between stores. X86/pr40631_deadstore_elision -- folds constant byte store into preceding quad word constant store. Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet Reviewed By: courbet Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59260 llvm-svn: 356068
2019-03-14 01:07:09 +08:00
; CHECK-DAG: str r3, [sp, #12]
; CHECK-DAG: str r2, [sp, #8]
ARM: Correctly align arguments after a byval struct is passed on the stack llvm-svn: 202985
2014-03-05 23:25:27 +08:00
; CHECK: bl usePtr
; CHECK: pop {r11, lr}
; CHECK: add sp, sp, #8
ARM: enable tail call optimisation on Thumb 2 Tail call optimisation was previously disabled on all targets other than iOS5.0+. This enables the tail call optimisation on all Thumb 2 capable platforms. The test adjustments are to remove the IR hint "tail" to function invocation. The tests were designed assuming that tail call optimisations would not kick in which no longer holds true. llvm-svn: 203575
2014-03-11 23:09:44 +08:00
call void @usePtr(%struct8bytes8align* %b)
ARM: Correctly align arguments after a byval struct is passed on the stack llvm-svn: 202985
2014-03-05 23:25:27 +08:00
ret void
}
; a -> r0..r1
; b -> r2
define void @foo3(%struct8bytes8align* byval %a, %struct4bytes* byval %b) {
; CHECK-LABEL: foo3
; CHECK: sub sp, sp, #16
; CHECK: push {r11, lr}
; CHECK: add [[SCRATCH:r[0-9]+]], sp, #8
; CHECK: stm [[SCRATCH]], {r0, r1, r2}
; CHECK: add r0, sp, #8
; CHECK: bl usePtr
; CHECK: pop {r11, lr}
; CHECK: add sp, sp, #16
ARM: enable tail call optimisation on Thumb 2 Tail call optimisation was previously disabled on all targets other than iOS5.0+. This enables the tail call optimisation on all Thumb 2 capable platforms. The test adjustments are to remove the IR hint "tail" to function invocation. The tests were designed assuming that tail call optimisations would not kick in which no longer holds true. llvm-svn: 203575
2014-03-11 23:09:44 +08:00
call void @usePtr(%struct8bytes8align* %a)
ARM: Correctly align arguments after a byval struct is passed on the stack llvm-svn: 202985
2014-03-05 23:25:27 +08:00
ret void
}
; a -> r0
; b -> r2..r3
define void @foo4(%struct4bytes* byval %a, %struct8bytes8align* byval %b) {
; CHECK-LABEL: foo4
; CHECK: sub sp, sp, #16
; CHECK: push {r11, lr}
; CHECK: str r0, [sp, #8]
; CHECK: add r0, sp, #16
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later. Summary: A number of optimizations are inhibited by single-use TokenFactors not being merged into the TokenFactor using it. This makes we consider if we can do the merge immediately. Most tests changes here are due to the change in visitation causing minor reorderings and associated reassociation of paired memory operations. CodeGen tests with non-reordering changes: X86/aligned-variadic.ll -- memory-based add folded into stored leaq value. X86/constant-combiners.ll -- Optimizes out overlap between stores. X86/pr40631_deadstore_elision -- folds constant byte store into preceding quad word constant store. Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet Reviewed By: courbet Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59260 llvm-svn: 356068
2019-03-14 01:07:09 +08:00
; CHECK-DAG: str r3, [sp, #20]
; CHECK-DAG: str r2, [sp, #16]
ARM: Correctly align arguments after a byval struct is passed on the stack llvm-svn: 202985
2014-03-05 23:25:27 +08:00
; CHECK: bl usePtr
; CHECK: pop {r11, lr}
; CHECK: add sp, sp, #16
; CHECK: mov pc, lr
ARM: enable tail call optimisation on Thumb 2 Tail call optimisation was previously disabled on all targets other than iOS5.0+. This enables the tail call optimisation on all Thumb 2 capable platforms. The test adjustments are to remove the IR hint "tail" to function invocation. The tests were designed assuming that tail call optimisations would not kick in which no longer holds true. llvm-svn: 203575
2014-03-11 23:09:44 +08:00
call void @usePtr(%struct8bytes8align* %b)
ARM: Correctly align arguments after a byval struct is passed on the stack llvm-svn: 202985
2014-03-05 23:25:27 +08:00
ret void
}
; a -> r0..r1
; b -> r2
; c -> r3
define void @foo5(%struct8bytes8align* byval %a, %struct4bytes* byval %b, %struct4bytes* byval %c) {
; CHECK-LABEL: foo5
; CHECK: sub sp, sp, #16
; CHECK: push {r11, lr}
; CHECK: add [[SCRATCH:r[0-9]+]], sp, #8
; CHECK: stm [[SCRATCH]], {r0, r1, r2, r3}
; CHECK: add r0, sp, #8
; CHECK: bl usePtr
; CHECK: pop {r11, lr}
; CHECK: add sp, sp, #16
; CHECK: mov pc, lr
ARM: enable tail call optimisation on Thumb 2 Tail call optimisation was previously disabled on all targets other than iOS5.0+. This enables the tail call optimisation on all Thumb 2 capable platforms. The test adjustments are to remove the IR hint "tail" to function invocation. The tests were designed assuming that tail call optimisations would not kick in which no longer holds true. llvm-svn: 203575
2014-03-11 23:09:44 +08:00
call void @usePtr(%struct8bytes8align* %a)
ARM: Correctly align arguments after a byval struct is passed on the stack llvm-svn: 202985
2014-03-05 23:25:27 +08:00
ret void
}
; a..c -> r0..r2
; d -> sp+0..sp+7
define void @foo6(i32 %a, i32 %b, i32 %c, %struct8bytes8align* byval %d) {
; CHECK-LABEL: foo6
; CHECK: push {r11, lr}
; CHECK: add r0, sp, #8
; CHECK: bl usePtr
; CHECK: pop {r11, lr}
; CHECK: mov pc, lr
ARM: enable tail call optimisation on Thumb 2 Tail call optimisation was previously disabled on all targets other than iOS5.0+. This enables the tail call optimisation on all Thumb 2 capable platforms. The test adjustments are to remove the IR hint "tail" to function invocation. The tests were designed assuming that tail call optimisations would not kick in which no longer holds true. llvm-svn: 203575
2014-03-11 23:09:44 +08:00
call void @usePtr(%struct8bytes8align* %d)
ARM: Correctly align arguments after a byval struct is passed on the stack llvm-svn: 202985
2014-03-05 23:25:27 +08:00
ret void
}