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llvm-project/llvm/test/CodeGen/X86/TruncAssertSext.ll

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[X86] Add an extra instruction to TruncAssertSext.ll to prevent the 'or' from being narrowed so that the movl is really required to avoid a miscompile. If we allow the OR to be narrowed then the upper bits really are zero and we can't tell if the zeroing movl was removed on purpose. While here regenerate the test with update_llc_test_checks.py llvm-svn: 312995
2017-09-12 11:50:44 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -O2 -mtriple=x86_64-unknown-unknown | FileCheck %s
Fix CR/LF line endings in test case. llvm-svn: 222120
2014-11-17 16:00:45 +08:00
; Checks that a zeroing mov is inserted for the trunc/zext pair even when
; the source of the zext is an AssertSext node
; PR20494
define i64 @main(i64 %a) {
[X86] Add an extra instruction to TruncAssertSext.ll to prevent the 'or' from being narrowed so that the movl is really required to avoid a miscompile. If we allow the OR to be narrowed then the upper bits really are zero and we can't tell if the zeroing movl was removed on purpose. While here regenerate the test with update_llc_test_checks.py llvm-svn: 312995
2017-09-12 11:50:44 +08:00
; CHECK-LABEL: main:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0:
[X86] Add an extra instruction to TruncAssertSext.ll to prevent the 'or' from being narrowed so that the movl is really required to avoid a miscompile. If we allow the OR to be narrowed then the upper bits really are zero and we can't tell if the zeroing movl was removed on purpose. While here regenerate the test with update_llc_test_checks.py llvm-svn: 312995
2017-09-12 11:50:44 +08:00
; CHECK-NEXT: orq $-2, %rdi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
Fix CR/LF line endings in test case. llvm-svn: 222120
2014-11-17 16:00:45 +08:00
%or = or i64 %a, -2
%trunc = trunc i64 %or to i32
br label %l
l:
%ext = zext i32 %trunc to i64
[X86] Add an extra instruction to TruncAssertSext.ll to prevent the 'or' from being narrowed so that the movl is really required to avoid a miscompile. If we allow the OR to be narrowed then the upper bits really are zero and we can't tell if the zeroing movl was removed on purpose. While here regenerate the test with update_llc_test_checks.py llvm-svn: 312995
2017-09-12 11:50:44 +08:00
trunc i64 %or to i32 ; to keep the or from being narrowed
Fix CR/LF line endings in test case. llvm-svn: 222120
2014-11-17 16:00:45 +08:00
ret i64 %ext
}