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llvm-project/llvm/test/Transforms/ScalarRepl/vector_promote.ll

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Change tests from "opt %s" to "opt < %s" so that opt doesn't see the input filename so that opt doesn't print the input filename in the output so that grep lines in the tests don't unintentionally match strings in the input filename. llvm-svn: 81537
2009-09-12 02:01:28 +08:00
; RUN: opt < %s -scalarrepl -S | not grep alloca
; RUN: opt < %s -scalarrepl -S | grep {load <4 x float>}
Make opt default to not adding a target data string and update tests that depend on target data to supply it within the test llvm-svn: 85900
2009-11-03 23:29:06 +08:00
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
New testcase, checking to see we can turn this code: void test(vector float *F, float f) { vector float G = *F + *F; *((float*)&G) = f; *F = G + G; } void test2(vector float *F, float f) { vector float G = *F + *F; ((float*)&G)[2] = f; *F = G + G; } void test3(vector float *F, float *f) { vector float G = *F + *F; *f = ((float*)&G)[2]; } void test4(vector float *F, float *f) { vector float G = *F + *F; *f = *((float*)&G); } into insert/extract element operations with no memory traffic. llvm-svn: 27709
2006-04-15 05:41:54 +08:00
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
define void @test(<4 x float>* %F, float %f) {
New testcase, checking to see we can turn this code: void test(vector float *F, float f) { vector float G = *F + *F; *((float*)&G) = f; *F = G + G; } void test2(vector float *F, float f) { vector float G = *F + *F; ((float*)&G)[2] = f; *F = G + G; } void test3(vector float *F, float *f) { vector float G = *F + *F; *f = ((float*)&G)[2]; } void test4(vector float *F, float *f) { vector float G = *F + *F; *f = *((float*)&G); } into insert/extract element operations with no memory traffic. llvm-svn: 27709
2006-04-15 05:41:54 +08:00
entry:
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
%G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=3]
%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
store <4 x float> %tmp3, <4 x float>* %G
%G.upgrd.1 = getelementptr <4 x float>* %G, i32 0, i32 0 ; <float*> [#uses=1]
store float %f, float* %G.upgrd.1
%tmp4 = load <4 x float>* %G ; <<4 x float>> [#uses=2]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%tmp6 = fadd <4 x float> %tmp4, %tmp4 ; <<4 x float>> [#uses=1]
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
store <4 x float> %tmp6, <4 x float>* %F
ret void
New testcase, checking to see we can turn this code: void test(vector float *F, float f) { vector float G = *F + *F; *((float*)&G) = f; *F = G + G; } void test2(vector float *F, float f) { vector float G = *F + *F; ((float*)&G)[2] = f; *F = G + G; } void test3(vector float *F, float *f) { vector float G = *F + *F; *f = ((float*)&G)[2]; } void test4(vector float *F, float *f) { vector float G = *F + *F; *f = *((float*)&G); } into insert/extract element operations with no memory traffic. llvm-svn: 27709
2006-04-15 05:41:54 +08:00
}
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
define void @test2(<4 x float>* %F, float %f) {
New testcase, checking to see we can turn this code: void test(vector float *F, float f) { vector float G = *F + *F; *((float*)&G) = f; *F = G + G; } void test2(vector float *F, float f) { vector float G = *F + *F; ((float*)&G)[2] = f; *F = G + G; } void test3(vector float *F, float *f) { vector float G = *F + *F; *f = ((float*)&G)[2]; } void test4(vector float *F, float *f) { vector float G = *F + *F; *f = *((float*)&G); } into insert/extract element operations with no memory traffic. llvm-svn: 27709
2006-04-15 05:41:54 +08:00
entry:
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
%G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=3]
%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
store <4 x float> %tmp3, <4 x float>* %G
%tmp.upgrd.2 = getelementptr <4 x float>* %G, i32 0, i32 2 ; <float*> [#uses=1]
store float %f, float* %tmp.upgrd.2
%tmp4 = load <4 x float>* %G ; <<4 x float>> [#uses=2]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%tmp6 = fadd <4 x float> %tmp4, %tmp4 ; <<4 x float>> [#uses=1]
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
store <4 x float> %tmp6, <4 x float>* %F
ret void
New testcase, checking to see we can turn this code: void test(vector float *F, float f) { vector float G = *F + *F; *((float*)&G) = f; *F = G + G; } void test2(vector float *F, float f) { vector float G = *F + *F; ((float*)&G)[2] = f; *F = G + G; } void test3(vector float *F, float *f) { vector float G = *F + *F; *f = ((float*)&G)[2]; } void test4(vector float *F, float *f) { vector float G = *F + *F; *f = *((float*)&G); } into insert/extract element operations with no memory traffic. llvm-svn: 27709
2006-04-15 05:41:54 +08:00
}
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
define void @test3(<4 x float>* %F, float* %f) {
New testcase, checking to see we can turn this code: void test(vector float *F, float f) { vector float G = *F + *F; *((float*)&G) = f; *F = G + G; } void test2(vector float *F, float f) { vector float G = *F + *F; ((float*)&G)[2] = f; *F = G + G; } void test3(vector float *F, float *f) { vector float G = *F + *F; *f = ((float*)&G)[2]; } void test4(vector float *F, float *f) { vector float G = *F + *F; *f = *((float*)&G); } into insert/extract element operations with no memory traffic. llvm-svn: 27709
2006-04-15 05:41:54 +08:00
entry:
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
%G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=2]
%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
store <4 x float> %tmp3, <4 x float>* %G
%tmp.upgrd.3 = getelementptr <4 x float>* %G, i32 0, i32 2 ; <float*> [#uses=1]
%tmp.upgrd.4 = load float* %tmp.upgrd.3 ; <float> [#uses=1]
store float %tmp.upgrd.4, float* %f
ret void
New testcase, checking to see we can turn this code: void test(vector float *F, float f) { vector float G = *F + *F; *((float*)&G) = f; *F = G + G; } void test2(vector float *F, float f) { vector float G = *F + *F; ((float*)&G)[2] = f; *F = G + G; } void test3(vector float *F, float *f) { vector float G = *F + *F; *f = ((float*)&G)[2]; } void test4(vector float *F, float *f) { vector float G = *F + *F; *f = *((float*)&G); } into insert/extract element operations with no memory traffic. llvm-svn: 27709
2006-04-15 05:41:54 +08:00
}
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
define void @test4(<4 x float>* %F, float* %f) {
New testcase, checking to see we can turn this code: void test(vector float *F, float f) { vector float G = *F + *F; *((float*)&G) = f; *F = G + G; } void test2(vector float *F, float f) { vector float G = *F + *F; ((float*)&G)[2] = f; *F = G + G; } void test3(vector float *F, float *f) { vector float G = *F + *F; *f = ((float*)&G)[2]; } void test4(vector float *F, float *f) { vector float G = *F + *F; *f = *((float*)&G); } into insert/extract element operations with no memory traffic. llvm-svn: 27709
2006-04-15 05:41:54 +08:00
entry:
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
%G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=2]
%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
Upgrade tests to not use llvm-upgrade. llvm-svn: 48484
2008-03-18 12:14:37 +08:00
store <4 x float> %tmp3, <4 x float>* %G
%G.upgrd.5 = getelementptr <4 x float>* %G, i32 0, i32 0 ; <float*> [#uses=1]
%tmp.upgrd.6 = load float* %G.upgrd.5 ; <float> [#uses=1]
store float %tmp.upgrd.6, float* %f
ret void
New testcase, checking to see we can turn this code: void test(vector float *F, float f) { vector float G = *F + *F; *((float*)&G) = f; *F = G + G; } void test2(vector float *F, float f) { vector float G = *F + *F; ((float*)&G)[2] = f; *F = G + G; } void test3(vector float *F, float *f) { vector float G = *F + *F; *f = ((float*)&G)[2]; } void test4(vector float *F, float *f) { vector float G = *F + *F; *f = *((float*)&G); } into insert/extract element operations with no memory traffic. llvm-svn: 27709
2006-04-15 05:41:54 +08:00
}
rearrange how SRoA handles promotion of allocas to vectors. With the new world order, it can handle cases where the first store into the alloca is an element of the vector, instead of requiring the first analyzed store to have the vector type itself. This allows us to un-xfail test/CodeGen/X86/vec_ins_extract.ll. llvm-svn: 63590
2009-02-03 09:30:09 +08:00
define i32 @test5(float %X) { ;; should turn into bitcast.
%X_addr = alloca [4 x float]
%X1 = getelementptr [4 x float]* %X_addr, i32 0, i32 2
store float %X, float* %X1
%a = bitcast float* %X1 to i32*
%tmp = load i32* %a
ret i32 %tmp
}