2016-04-02 04:55:19 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X64
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2015-02-03 06:00:48 +08:00
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2016-04-02 04:55:19 +08:00
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define i32 @test0(<1 x i64>* %v4) nounwind {
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; X32-LABEL: test0:
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; X32: # BB#0: # %entry
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; X32-NEXT: pushl %ebp
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; X32-NEXT: movl %esp, %ebp
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; X32-NEXT: andl $-8, %esp
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; X32-NEXT: subl $24, %esp
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; X32-NEXT: movl 8(%ebp), %eax
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; X32-NEXT: movl (%eax), %ecx
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; X32-NEXT: movl 4(%eax), %eax
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; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; X32-NEXT: movl %ecx, (%esp)
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; X32-NEXT: pshufw $238, (%esp), %mm0 # mm0 = mem[2,3,2,3]
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; X32-NEXT: movq %mm0, {{[0-9]+}}(%esp)
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2017-02-28 05:01:57 +08:00
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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2016-04-02 04:55:19 +08:00
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; X32-NEXT: addl $32, %eax
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; X32-NEXT: movl %ebp, %esp
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; X32-NEXT: popl %ebp
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; X32-NEXT: retl
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;
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; X64-LABEL: test0:
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; X64: # BB#0: # %entry
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; X64-NEXT: pshufw $238, (%rdi), %mm0 # mm0 = mem[2,3,2,3]
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; X64-NEXT: movd %mm0, %eax
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; X64-NEXT: addl $32, %eax
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; X64-NEXT: retq
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2015-02-26 23:10:38 +08:00
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entry:
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2015-02-28 05:17:42 +08:00
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%v5 = load <1 x i64>, <1 x i64>* %v4, align 8
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2015-02-03 06:00:48 +08:00
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%v12 = bitcast <1 x i64> %v5 to <4 x i16>
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%v13 = bitcast <4 x i16> %v12 to x86_mmx
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%v14 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v13, i8 -18)
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%v15 = bitcast x86_mmx %v14 to <4 x i16>
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%v16 = bitcast <4 x i16> %v15 to <1 x i64>
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%v17 = extractelement <1 x i64> %v16, i32 0
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%v18 = bitcast i64 %v17 to <2 x i32>
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%v19 = extractelement <2 x i32> %v18, i32 0
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%v20 = add i32 %v19, 32
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ret i32 %v20
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}
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2016-04-02 04:55:19 +08:00
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define i32 @test1(i32* nocapture readonly %ptr) nounwind {
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; X32-LABEL: test1:
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; X32: # BB#0: # %entry
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; X32-NEXT: pushl %ebp
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; X32-NEXT: movl %esp, %ebp
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; X32-NEXT: andl $-8, %esp
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; X32-NEXT: subl $16, %esp
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; X32-NEXT: movl 8(%ebp), %eax
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; X32-NEXT: movd (%eax), %mm0
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; X32-NEXT: pshufw $232, %mm0, %mm0 # mm0 = mm0[0,2,2,3]
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; X32-NEXT: movq %mm0, (%esp)
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2017-02-28 05:01:57 +08:00
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; X32-NEXT: movl (%esp), %eax
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2016-04-02 04:55:19 +08:00
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; X32-NEXT: emms
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; X32-NEXT: movl %ebp, %esp
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; X32-NEXT: popl %ebp
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; X32-NEXT: retl
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;
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; X64-LABEL: test1:
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; X64: # BB#0: # %entry
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; X64-NEXT: movd (%rdi), %mm0
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; X64-NEXT: pshufw $232, %mm0, %mm0 # mm0 = mm0[0,2,2,3]
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; X64-NEXT: movd %mm0, %eax
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; X64-NEXT: emms
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; X64-NEXT: retq
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2015-02-03 06:00:48 +08:00
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entry:
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2015-02-28 05:17:42 +08:00
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%0 = load i32, i32* %ptr, align 4
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2015-02-03 06:00:48 +08:00
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%1 = insertelement <2 x i32> undef, i32 %0, i32 0
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%2 = insertelement <2 x i32> %1, i32 0, i32 1
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%3 = bitcast <2 x i32> %2 to x86_mmx
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%4 = bitcast x86_mmx %3 to i64
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%5 = bitcast i64 %4 to <4 x i16>
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%6 = bitcast <4 x i16> %5 to x86_mmx
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%7 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %6, i8 -24)
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%8 = bitcast x86_mmx %7 to <4 x i16>
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%9 = bitcast <4 x i16> %8 to <1 x i64>
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%10 = extractelement <1 x i64> %9, i32 0
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%11 = bitcast i64 %10 to <2 x i32>
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%12 = extractelement <2 x i32> %11, i32 0
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tail call void @llvm.x86.mmx.emms()
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ret i32 %12
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}
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2016-04-02 04:55:19 +08:00
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define i32 @test2(i32* nocapture readonly %ptr) nounwind {
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; X32-LABEL: test2:
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; X32: # BB#0: # %entry
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; X32-NEXT: pushl %ebp
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; X32-NEXT: movl %esp, %ebp
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; X32-NEXT: andl $-8, %esp
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; X32-NEXT: subl $16, %esp
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; X32-NEXT: movl 8(%ebp), %eax
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; X32-NEXT: pshufw $232, (%eax), %mm0 # mm0 = mem[0,2,2,3]
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; X32-NEXT: movq %mm0, (%esp)
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2017-02-28 05:01:57 +08:00
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; X32-NEXT: movl (%esp), %eax
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2016-04-02 04:55:19 +08:00
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; X32-NEXT: emms
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; X32-NEXT: movl %ebp, %esp
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; X32-NEXT: popl %ebp
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; X32-NEXT: retl
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;
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; X64-LABEL: test2:
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; X64: # BB#0: # %entry
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; X64-NEXT: pshufw $232, (%rdi), %mm0 # mm0 = mem[0,2,2,3]
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; X64-NEXT: movd %mm0, %eax
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; X64-NEXT: emms
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; X64-NEXT: retq
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2015-02-03 06:00:48 +08:00
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entry:
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%0 = bitcast i32* %ptr to x86_mmx*
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2015-02-28 05:17:42 +08:00
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%1 = load x86_mmx, x86_mmx* %0, align 8
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2015-02-03 06:00:48 +08:00
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%2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -24)
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%3 = bitcast x86_mmx %2 to <4 x i16>
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%4 = bitcast <4 x i16> %3 to <1 x i64>
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%5 = extractelement <1 x i64> %4, i32 0
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%6 = bitcast i64 %5 to <2 x i32>
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%7 = extractelement <2 x i32> %6, i32 0
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tail call void @llvm.x86.mmx.emms()
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ret i32 %7
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}
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2016-04-27 09:35:25 +08:00
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define i32 @test3(x86_mmx %a) nounwind {
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; X32-LABEL: test3:
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; X32: # BB#0:
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; X32-NEXT: movd %mm0, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test3:
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; X64: # BB#0:
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; X64-NEXT: movd %mm0, %eax
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; X64-NEXT: retq
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%tmp0 = bitcast x86_mmx %a to <2 x i32>
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%tmp1 = extractelement <2 x i32> %tmp0, i32 0
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ret i32 %tmp1
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}
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2016-04-27 09:35:29 +08:00
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; Verify we don't muck with extractelts from the upper lane.
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define i32 @test4(x86_mmx %a) nounwind {
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; X32-LABEL: test4:
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; X32: # BB#0:
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; X32-NEXT: pushl %ebp
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; X32-NEXT: movl %esp, %ebp
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; X32-NEXT: andl $-8, %esp
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; X32-NEXT: subl $8, %esp
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; X32-NEXT: movq %mm0, (%esp)
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2016-12-18 22:26:02 +08:00
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; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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2017-02-16 01:41:33 +08:00
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; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,0,1]
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2016-04-27 09:35:29 +08:00
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; X32-NEXT: movd %xmm0, %eax
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; X32-NEXT: movl %ebp, %esp
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; X32-NEXT: popl %ebp
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; X32-NEXT: retl
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;
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; X64-LABEL: test4:
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; X64: # BB#0:
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; X64-NEXT: movq %mm0, -{{[0-9]+}}(%rsp)
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; X64-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,0,1]
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; X64-NEXT: movd %xmm0, %eax
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; X64-NEXT: retq
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%tmp0 = bitcast x86_mmx %a to <2 x i32>
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%tmp1 = extractelement <2 x i32> %tmp0, i32 1
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ret i32 %tmp1
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}
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2015-02-03 06:00:48 +08:00
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declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
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declare void @llvm.x86.mmx.emms()
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