2015-06-30 07:51:55 +08:00
|
|
|
// WebAssemblyInstrAtomics.td-WebAssembly Atomic codegen support-*- tablegen -*-
|
|
|
|
//
|
2019-01-19 16:50:56 +08:00
|
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
2015-06-30 07:51:55 +08:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
2015-07-11 02:23:10 +08:00
|
|
|
///
|
|
|
|
/// \file
|
2018-05-01 23:54:18 +08:00
|
|
|
/// WebAssembly Atomic operand code-gen constructs.
|
2015-07-11 02:23:10 +08:00
|
|
|
///
|
2015-06-30 07:51:55 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
[WebAssembly] Use named operands to identify loads and stores
Summary:
Uses the named operands tablegen feature to look up the indices of
offset, address, and p2align operands for all load and store
instructions. This replaces brittle, incorrect logic for identifying
loads and store when eliminating frame indices, which previously
crashed on bulk-memory ops. It also cleans up the SetP2Alignment pass.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59007
llvm-svn: 355770
2019-03-09 12:31:37 +08:00
|
|
|
let UseNamedOperandTable = 1 in
|
2019-02-20 09:29:34 +08:00
|
|
|
multiclass ATOMIC_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
|
|
|
|
list<dag> pattern_r, string asmstr_r = "",
|
|
|
|
string asmstr_s = "", bits<32> atomic_op = -1> {
|
|
|
|
defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
|
|
|
|
!or(0xfe00, !and(0xff, atomic_op))>,
|
|
|
|
Requires<[HasAtomics]>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass ATOMIC_NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
|
|
|
|
bits<32> atomic_op = -1> {
|
|
|
|
defm "" : NRI<oops, iops, pattern, asmstr,
|
|
|
|
!or(0xfe00, !and(0xff, atomic_op))>,
|
|
|
|
Requires<[HasAtomics]>;
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Atomic wait / notify
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
let hasSideEffects = 1 in {
|
|
|
|
defm ATOMIC_NOTIFY :
|
|
|
|
ATOMIC_I<(outs I32:$dst),
|
|
|
|
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$count),
|
|
|
|
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
|
|
|
|
"atomic.notify \t$dst, ${off}(${addr})${p2align}, $count",
|
|
|
|
"atomic.notify \t${off}${p2align}", 0x00>;
|
|
|
|
let mayLoad = 1 in {
|
|
|
|
defm ATOMIC_WAIT_I32 :
|
|
|
|
ATOMIC_I<(outs I32:$dst),
|
|
|
|
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$exp,
|
|
|
|
I64:$timeout),
|
|
|
|
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
|
|
|
|
"i32.atomic.wait \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
|
|
|
|
"i32.atomic.wait \t${off}${p2align}", 0x01>;
|
|
|
|
defm ATOMIC_WAIT_I64 :
|
|
|
|
ATOMIC_I<(outs I32:$dst),
|
|
|
|
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, I64:$exp,
|
|
|
|
I64:$timeout),
|
|
|
|
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
|
|
|
|
"i64.atomic.wait \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
|
|
|
|
"i64.atomic.wait \t${off}${p2align}", 0x02>;
|
|
|
|
} // mayLoad = 1
|
|
|
|
} // hasSideEffects = 1
|
|
|
|
|
|
|
|
let Predicates = [HasAtomics] in {
|
|
|
|
// Select notifys with no constant offset.
|
|
|
|
def NotifyPatNoOffset :
|
|
|
|
Pat<(i32 (int_wasm_atomic_notify I32:$addr, I32:$count)),
|
|
|
|
(ATOMIC_NOTIFY 0, 0, I32:$addr, I32:$count)>;
|
|
|
|
|
|
|
|
// Select notifys with a constant offset.
|
|
|
|
|
|
|
|
// Pattern with address + immediate offset
|
|
|
|
class NotifyPatImmOff<PatFrag operand> :
|
|
|
|
Pat<(i32 (int_wasm_atomic_notify (operand I32:$addr, imm:$off), I32:$count)),
|
|
|
|
(ATOMIC_NOTIFY 0, imm:$off, I32:$addr, I32:$count)>;
|
|
|
|
def : NotifyPatImmOff<regPlusImm>;
|
|
|
|
def : NotifyPatImmOff<or_is_add>;
|
|
|
|
|
|
|
|
def NotifyPatGlobalAddr :
|
|
|
|
Pat<(i32 (int_wasm_atomic_notify (regPlusGA I32:$addr,
|
|
|
|
(WebAssemblywrapper tglobaladdr:$off)),
|
|
|
|
I32:$count)),
|
|
|
|
(ATOMIC_NOTIFY 0, tglobaladdr:$off, I32:$addr, I32:$count)>;
|
|
|
|
|
|
|
|
// Select notifys with just a constant offset.
|
|
|
|
def NotifyPatOffsetOnly :
|
|
|
|
Pat<(i32 (int_wasm_atomic_notify imm:$off, I32:$count)),
|
|
|
|
(ATOMIC_NOTIFY 0, imm:$off, (CONST_I32 0), I32:$count)>;
|
|
|
|
|
|
|
|
def NotifyPatGlobalAddrOffOnly :
|
|
|
|
Pat<(i32 (int_wasm_atomic_notify (WebAssemblywrapper tglobaladdr:$off),
|
|
|
|
I32:$count)),
|
|
|
|
(ATOMIC_NOTIFY 0, tglobaladdr:$off, (CONST_I32 0), I32:$count)>;
|
|
|
|
|
|
|
|
// Select waits with no constant offset.
|
|
|
|
class WaitPatNoOffset<ValueType ty, Intrinsic kind, NI inst> :
|
|
|
|
Pat<(i32 (kind I32:$addr, ty:$exp, I64:$timeout)),
|
|
|
|
(inst 0, 0, I32:$addr, ty:$exp, I64:$timeout)>;
|
|
|
|
def : WaitPatNoOffset<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
|
|
|
|
def : WaitPatNoOffset<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
|
|
|
|
|
|
|
|
// Select waits with a constant offset.
|
|
|
|
|
|
|
|
// Pattern with address + immediate offset
|
|
|
|
class WaitPatImmOff<ValueType ty, Intrinsic kind, PatFrag operand, NI inst> :
|
|
|
|
Pat<(i32 (kind (operand I32:$addr, imm:$off), ty:$exp, I64:$timeout)),
|
|
|
|
(inst 0, imm:$off, I32:$addr, ty:$exp, I64:$timeout)>;
|
|
|
|
def : WaitPatImmOff<i32, int_wasm_atomic_wait_i32, regPlusImm, ATOMIC_WAIT_I32>;
|
|
|
|
def : WaitPatImmOff<i32, int_wasm_atomic_wait_i32, or_is_add, ATOMIC_WAIT_I32>;
|
|
|
|
def : WaitPatImmOff<i64, int_wasm_atomic_wait_i64, regPlusImm, ATOMIC_WAIT_I64>;
|
|
|
|
def : WaitPatImmOff<i64, int_wasm_atomic_wait_i64, or_is_add, ATOMIC_WAIT_I64>;
|
|
|
|
|
|
|
|
class WaitPatGlobalAddr<ValueType ty, Intrinsic kind, NI inst> :
|
|
|
|
Pat<(i32 (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
|
|
|
|
ty:$exp, I64:$timeout)),
|
|
|
|
(inst 0, tglobaladdr:$off, I32:$addr, ty:$exp, I64:$timeout)>;
|
|
|
|
def : WaitPatGlobalAddr<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
|
|
|
|
def : WaitPatGlobalAddr<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
|
|
|
|
|
|
|
|
// Select wait_i32, ATOMIC_WAIT_I32s with just a constant offset.
|
|
|
|
class WaitPatOffsetOnly<ValueType ty, Intrinsic kind, NI inst> :
|
|
|
|
Pat<(i32 (kind imm:$off, ty:$exp, I64:$timeout)),
|
|
|
|
(inst 0, imm:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>;
|
|
|
|
def : WaitPatOffsetOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
|
|
|
|
def : WaitPatOffsetOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
|
|
|
|
|
|
|
|
class WaitPatGlobalAddrOffOnly<ValueType ty, Intrinsic kind, NI inst> :
|
|
|
|
Pat<(i32 (kind (WebAssemblywrapper tglobaladdr:$off), ty:$exp, I64:$timeout)),
|
|
|
|
(inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>;
|
|
|
|
def : WaitPatGlobalAddrOffOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
|
|
|
|
def : WaitPatGlobalAddrOffOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
|
|
|
|
} // Predicates = [HasAtomics]
|
|
|
|
|
2015-06-30 07:51:55 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Atomic loads
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2019-02-20 09:29:34 +08:00
|
|
|
multiclass AtomicLoad<WebAssemblyRegClass rc, string name, int atomic_op> {
|
|
|
|
defm "" : WebAssemblyLoad<rc, name, !or(0xfe00, !and(0xff, atomic_op))>,
|
2018-08-23 08:36:43 +08:00
|
|
|
Requires<[HasAtomics]>;
|
|
|
|
}
|
|
|
|
|
2019-02-20 09:29:34 +08:00
|
|
|
defm ATOMIC_LOAD_I32 : AtomicLoad<I32, "i32.atomic.load", 0x10>;
|
|
|
|
defm ATOMIC_LOAD_I64 : AtomicLoad<I64, "i64.atomic.load", 0x11>;
|
2017-08-31 02:07:45 +08:00
|
|
|
|
|
|
|
// Select loads with no constant offset.
|
|
|
|
let Predicates = [HasAtomics] in {
|
2017-10-06 05:18:42 +08:00
|
|
|
def : LoadPatNoOffset<i32, atomic_load_32, ATOMIC_LOAD_I32>;
|
|
|
|
def : LoadPatNoOffset<i64, atomic_load_64, ATOMIC_LOAD_I64>;
|
2017-09-01 05:51:48 +08:00
|
|
|
|
2017-10-06 05:18:42 +08:00
|
|
|
// Select loads with a constant offset.
|
|
|
|
|
|
|
|
// Pattern with address + immediate offset
|
|
|
|
def : LoadPatImmOff<i32, atomic_load_32, regPlusImm, ATOMIC_LOAD_I32>;
|
|
|
|
def : LoadPatImmOff<i64, atomic_load_64, regPlusImm, ATOMIC_LOAD_I64>;
|
|
|
|
def : LoadPatImmOff<i32, atomic_load_32, or_is_add, ATOMIC_LOAD_I32>;
|
|
|
|
def : LoadPatImmOff<i64, atomic_load_64, or_is_add, ATOMIC_LOAD_I64>;
|
|
|
|
|
|
|
|
def : LoadPatGlobalAddr<i32, atomic_load_32, ATOMIC_LOAD_I32>;
|
|
|
|
def : LoadPatGlobalAddr<i64, atomic_load_64, ATOMIC_LOAD_I64>;
|
|
|
|
|
|
|
|
// Select loads with just a constant offset.
|
|
|
|
def : LoadPatOffsetOnly<i32, atomic_load_32, ATOMIC_LOAD_I32>;
|
|
|
|
def : LoadPatOffsetOnly<i64, atomic_load_64, ATOMIC_LOAD_I64>;
|
|
|
|
|
|
|
|
def : LoadPatGlobalAddrOffOnly<i32, atomic_load_32, ATOMIC_LOAD_I32>;
|
|
|
|
def : LoadPatGlobalAddrOffOnly<i64, atomic_load_64, ATOMIC_LOAD_I64>;
|
|
|
|
|
|
|
|
} // Predicates = [HasAtomics]
|
|
|
|
|
|
|
|
// Extending loads. Note that there are only zero-extending atomic loads, no
|
|
|
|
// sign-extending loads.
|
2019-02-20 09:29:34 +08:00
|
|
|
defm ATOMIC_LOAD8_U_I32 : AtomicLoad<I32, "i32.atomic.load8_u", 0x12>;
|
|
|
|
defm ATOMIC_LOAD16_U_I32 : AtomicLoad<I32, "i32.atomic.load16_u", 0x13>;
|
|
|
|
defm ATOMIC_LOAD8_U_I64 : AtomicLoad<I64, "i64.atomic.load8_u", 0x14>;
|
|
|
|
defm ATOMIC_LOAD16_U_I64 : AtomicLoad<I64, "i64.atomic.load16_u", 0x15>;
|
|
|
|
defm ATOMIC_LOAD32_U_I64 : AtomicLoad<I64, "i64.atomic.load32_u", 0x16>;
|
2017-10-06 05:18:42 +08:00
|
|
|
|
2018-07-10 04:18:21 +08:00
|
|
|
// Fragments for extending loads. These are different from regular loads because
|
2017-10-06 05:18:42 +08:00
|
|
|
// the SDNodes are derived from AtomicSDNode rather than LoadSDNode and
|
|
|
|
// therefore don't have the extension type field. So instead of matching that,
|
|
|
|
// we match the patterns that the type legalizer expands them to.
|
|
|
|
|
|
|
|
// We directly match zext patterns and select the zext atomic loads.
|
|
|
|
// i32 (zext (i8 (atomic_load_8))) gets legalized to
|
|
|
|
// i32 (and (i32 (atomic_load_8)), 255)
|
|
|
|
// These can be selected to a single zero-extending atomic load instruction.
|
2018-07-10 04:18:21 +08:00
|
|
|
def zext_aload_8_32 :
|
|
|
|
PatFrag<(ops node:$addr), (and (i32 (atomic_load_8 node:$addr)), 255)>;
|
|
|
|
def zext_aload_16_32 :
|
|
|
|
PatFrag<(ops node:$addr), (and (i32 (atomic_load_16 node:$addr)), 65535)>;
|
2017-10-06 05:18:42 +08:00
|
|
|
// Unlike regular loads, extension to i64 is handled differently than i32.
|
|
|
|
// i64 (zext (i8 (atomic_load_8))) gets legalized to
|
|
|
|
// i64 (and (i64 (anyext (i32 (atomic_load_8)))), 255)
|
|
|
|
def zext_aload_8_64 :
|
|
|
|
PatFrag<(ops node:$addr),
|
|
|
|
(and (i64 (anyext (i32 (atomic_load_8 node:$addr)))), 255)>;
|
|
|
|
def zext_aload_16_64 :
|
|
|
|
PatFrag<(ops node:$addr),
|
|
|
|
(and (i64 (anyext (i32 (atomic_load_16 node:$addr)))), 65535)>;
|
|
|
|
def zext_aload_32_64 :
|
|
|
|
PatFrag<(ops node:$addr),
|
|
|
|
(zext (i32 (atomic_load node:$addr)))>;
|
|
|
|
|
|
|
|
// We don't have single sext atomic load instructions. So for sext loads, we
|
|
|
|
// match bare subword loads (for 32-bit results) and anyext loads (for 64-bit
|
|
|
|
// results) and select a zext load; the next instruction will be sext_inreg
|
|
|
|
// which is selected by itself.
|
2018-07-10 04:18:21 +08:00
|
|
|
def sext_aload_8_64 :
|
2017-10-06 05:18:42 +08:00
|
|
|
PatFrag<(ops node:$addr), (anyext (i32 (atomic_load_8 node:$addr)))>;
|
2018-07-10 04:18:21 +08:00
|
|
|
def sext_aload_16_64 :
|
2017-10-06 05:18:42 +08:00
|
|
|
PatFrag<(ops node:$addr), (anyext (i32 (atomic_load_16 node:$addr)))>;
|
|
|
|
|
|
|
|
let Predicates = [HasAtomics] in {
|
|
|
|
// Select zero-extending loads with no constant offset.
|
2018-07-10 04:18:21 +08:00
|
|
|
def : LoadPatNoOffset<i32, zext_aload_8_32, ATOMIC_LOAD8_U_I32>;
|
|
|
|
def : LoadPatNoOffset<i32, zext_aload_16_32, ATOMIC_LOAD16_U_I32>;
|
2017-10-06 05:18:42 +08:00
|
|
|
def : LoadPatNoOffset<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
|
|
|
|
def : LoadPatNoOffset<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
|
|
|
|
def : LoadPatNoOffset<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
|
|
|
|
|
|
|
|
// Select sign-extending loads with no constant offset
|
|
|
|
def : LoadPatNoOffset<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
|
|
|
|
def : LoadPatNoOffset<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
|
2018-07-10 04:18:21 +08:00
|
|
|
def : LoadPatNoOffset<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>;
|
|
|
|
def : LoadPatNoOffset<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>;
|
2019-01-08 14:25:55 +08:00
|
|
|
// 32->64 sext load gets selected as i32.atomic.load, i64.extend_i32_s
|
2017-10-06 05:18:42 +08:00
|
|
|
|
|
|
|
// Zero-extending loads with constant offset
|
2018-07-10 04:18:21 +08:00
|
|
|
def : LoadPatImmOff<i32, zext_aload_8_32, regPlusImm, ATOMIC_LOAD8_U_I32>;
|
|
|
|
def : LoadPatImmOff<i32, zext_aload_16_32, regPlusImm, ATOMIC_LOAD16_U_I32>;
|
|
|
|
def : LoadPatImmOff<i32, zext_aload_8_32, or_is_add, ATOMIC_LOAD8_U_I32>;
|
|
|
|
def : LoadPatImmOff<i32, zext_aload_16_32, or_is_add, ATOMIC_LOAD16_U_I32>;
|
2017-10-06 05:18:42 +08:00
|
|
|
def : LoadPatImmOff<i64, zext_aload_8_64, regPlusImm, ATOMIC_LOAD8_U_I64>;
|
|
|
|
def : LoadPatImmOff<i64, zext_aload_16_64, regPlusImm, ATOMIC_LOAD16_U_I64>;
|
|
|
|
def : LoadPatImmOff<i64, zext_aload_32_64, regPlusImm, ATOMIC_LOAD32_U_I64>;
|
|
|
|
def : LoadPatImmOff<i64, zext_aload_8_64, or_is_add, ATOMIC_LOAD8_U_I64>;
|
|
|
|
def : LoadPatImmOff<i64, zext_aload_16_64, or_is_add, ATOMIC_LOAD16_U_I64>;
|
|
|
|
def : LoadPatImmOff<i64, zext_aload_32_64, or_is_add, ATOMIC_LOAD32_U_I64>;
|
|
|
|
|
|
|
|
// Sign-extending loads with constant offset
|
|
|
|
def : LoadPatImmOff<i32, atomic_load_8, regPlusImm, ATOMIC_LOAD8_U_I32>;
|
|
|
|
def : LoadPatImmOff<i32, atomic_load_16, regPlusImm, ATOMIC_LOAD16_U_I32>;
|
|
|
|
def : LoadPatImmOff<i32, atomic_load_8, or_is_add, ATOMIC_LOAD8_U_I32>;
|
|
|
|
def : LoadPatImmOff<i32, atomic_load_16, or_is_add, ATOMIC_LOAD16_U_I32>;
|
2018-07-10 04:18:21 +08:00
|
|
|
def : LoadPatImmOff<i64, sext_aload_8_64, regPlusImm, ATOMIC_LOAD8_U_I64>;
|
|
|
|
def : LoadPatImmOff<i64, sext_aload_16_64, regPlusImm, ATOMIC_LOAD16_U_I64>;
|
|
|
|
def : LoadPatImmOff<i64, sext_aload_8_64, or_is_add, ATOMIC_LOAD8_U_I64>;
|
|
|
|
def : LoadPatImmOff<i64, sext_aload_16_64, or_is_add, ATOMIC_LOAD16_U_I64>;
|
2017-10-06 05:18:42 +08:00
|
|
|
// No 32->64 patterns, just use i32.atomic.load and i64.extend_s/i64
|
|
|
|
|
2018-07-10 04:18:21 +08:00
|
|
|
def : LoadPatGlobalAddr<i32, zext_aload_8_32, ATOMIC_LOAD8_U_I32>;
|
|
|
|
def : LoadPatGlobalAddr<i32, zext_aload_16_32, ATOMIC_LOAD16_U_I32>;
|
2017-10-06 05:18:42 +08:00
|
|
|
def : LoadPatGlobalAddr<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
|
|
|
|
def : LoadPatGlobalAddr<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
|
|
|
|
def : LoadPatGlobalAddr<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
|
|
|
|
def : LoadPatGlobalAddr<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
|
|
|
|
def : LoadPatGlobalAddr<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
|
2018-07-10 04:18:21 +08:00
|
|
|
def : LoadPatGlobalAddr<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>;
|
|
|
|
def : LoadPatGlobalAddr<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>;
|
2017-10-06 05:18:42 +08:00
|
|
|
|
|
|
|
// Extending loads with just a constant offset
|
2018-07-10 04:18:21 +08:00
|
|
|
def : LoadPatOffsetOnly<i32, zext_aload_8_32, ATOMIC_LOAD8_U_I32>;
|
|
|
|
def : LoadPatOffsetOnly<i32, zext_aload_16_32, ATOMIC_LOAD16_U_I32>;
|
2017-10-06 05:18:42 +08:00
|
|
|
def : LoadPatOffsetOnly<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
|
|
|
|
def : LoadPatOffsetOnly<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
|
|
|
|
def : LoadPatOffsetOnly<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
|
|
|
|
def : LoadPatOffsetOnly<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
|
|
|
|
def : LoadPatOffsetOnly<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
|
2018-07-10 04:18:21 +08:00
|
|
|
def : LoadPatOffsetOnly<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>;
|
|
|
|
def : LoadPatOffsetOnly<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>;
|
2017-10-06 05:18:42 +08:00
|
|
|
|
2018-07-10 04:18:21 +08:00
|
|
|
def : LoadPatGlobalAddrOffOnly<i32, zext_aload_8_32, ATOMIC_LOAD8_U_I32>;
|
|
|
|
def : LoadPatGlobalAddrOffOnly<i32, zext_aload_16_32, ATOMIC_LOAD16_U_I32>;
|
2017-10-06 05:18:42 +08:00
|
|
|
def : LoadPatGlobalAddrOffOnly<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>;
|
|
|
|
def : LoadPatGlobalAddrOffOnly<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>;
|
|
|
|
def : LoadPatGlobalAddrOffOnly<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>;
|
|
|
|
def : LoadPatGlobalAddrOffOnly<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>;
|
|
|
|
def : LoadPatGlobalAddrOffOnly<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>;
|
2018-07-10 04:18:21 +08:00
|
|
|
def : LoadPatGlobalAddrOffOnly<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>;
|
|
|
|
def : LoadPatGlobalAddrOffOnly<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>;
|
2017-10-06 05:18:42 +08:00
|
|
|
|
|
|
|
} // Predicates = [HasAtomics]
|
2015-06-30 07:51:55 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Atomic stores
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2019-02-20 09:29:34 +08:00
|
|
|
multiclass AtomicStore<WebAssemblyRegClass rc, string name, int atomic_op> {
|
|
|
|
defm "" : WebAssemblyStore<rc, name, !or(0xfe00, !and(0xff, atomic_op))>,
|
|
|
|
Requires<[HasAtomics]>;
|
|
|
|
}
|
|
|
|
|
|
|
|
defm ATOMIC_STORE_I32 : AtomicStore<I32, "i32.atomic.store", 0x17>;
|
|
|
|
defm ATOMIC_STORE_I64 : AtomicStore<I64, "i64.atomic.store", 0x18>;
|
2018-07-03 05:22:59 +08:00
|
|
|
|
|
|
|
// We need an 'atomic' version of store patterns because store and atomic_store
|
|
|
|
// nodes have different operand orders:
|
|
|
|
// store: (store $val, $ptr)
|
|
|
|
// atomic_store: (store $ptr, $val)
|
|
|
|
|
|
|
|
let Predicates = [HasAtomics] in {
|
|
|
|
|
|
|
|
// Select stores with no constant offset.
|
2018-07-10 04:18:21 +08:00
|
|
|
class AStorePatNoOffset<ValueType ty, PatFrag kind, NI inst> :
|
|
|
|
Pat<(kind I32:$addr, ty:$val), (inst 0, 0, I32:$addr, ty:$val)>;
|
2018-07-03 05:22:59 +08:00
|
|
|
def : AStorePatNoOffset<i32, atomic_store_32, ATOMIC_STORE_I32>;
|
|
|
|
def : AStorePatNoOffset<i64, atomic_store_64, ATOMIC_STORE_I64>;
|
|
|
|
|
|
|
|
// Select stores with a constant offset.
|
|
|
|
|
|
|
|
// Pattern with address + immediate offset
|
2018-07-10 04:18:21 +08:00
|
|
|
class AStorePatImmOff<ValueType ty, PatFrag kind, PatFrag operand, NI inst> :
|
|
|
|
Pat<(kind (operand I32:$addr, imm:$off), ty:$val),
|
|
|
|
(inst 0, imm:$off, I32:$addr, ty:$val)>;
|
2018-07-03 05:22:59 +08:00
|
|
|
def : AStorePatImmOff<i32, atomic_store_32, regPlusImm, ATOMIC_STORE_I32>;
|
|
|
|
def : AStorePatImmOff<i64, atomic_store_64, regPlusImm, ATOMIC_STORE_I64>;
|
|
|
|
def : AStorePatImmOff<i32, atomic_store_32, or_is_add, ATOMIC_STORE_I32>;
|
|
|
|
def : AStorePatImmOff<i64, atomic_store_64, or_is_add, ATOMIC_STORE_I64>;
|
|
|
|
|
2018-07-10 04:18:21 +08:00
|
|
|
class AStorePatGlobalAddr<ValueType ty, PatFrag kind, NI inst> :
|
|
|
|
Pat<(kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
|
|
|
|
ty:$val),
|
2018-07-03 05:22:59 +08:00
|
|
|
(inst 0, tglobaladdr:$off, I32:$addr, ty:$val)>;
|
|
|
|
def : AStorePatGlobalAddr<i32, atomic_store_32, ATOMIC_STORE_I32>;
|
|
|
|
def : AStorePatGlobalAddr<i64, atomic_store_64, ATOMIC_STORE_I64>;
|
|
|
|
|
|
|
|
// Select stores with just a constant offset.
|
2018-07-10 04:18:21 +08:00
|
|
|
class AStorePatOffsetOnly<ValueType ty, PatFrag kind, NI inst> :
|
|
|
|
Pat<(kind imm:$off, ty:$val), (inst 0, imm:$off, (CONST_I32 0), ty:$val)>;
|
2018-07-03 05:22:59 +08:00
|
|
|
def : AStorePatOffsetOnly<i32, atomic_store_32, ATOMIC_STORE_I32>;
|
|
|
|
def : AStorePatOffsetOnly<i64, atomic_store_64, ATOMIC_STORE_I64>;
|
|
|
|
|
2018-07-10 04:18:21 +08:00
|
|
|
class AStorePatGlobalAddrOffOnly<ValueType ty, PatFrag kind, NI inst> :
|
|
|
|
Pat<(kind (WebAssemblywrapper tglobaladdr:$off), ty:$val),
|
2018-07-03 05:22:59 +08:00
|
|
|
(inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$val)>;
|
|
|
|
def : AStorePatGlobalAddrOffOnly<i32, atomic_store_32, ATOMIC_STORE_I32>;
|
|
|
|
def : AStorePatGlobalAddrOffOnly<i64, atomic_store_64, ATOMIC_STORE_I64>;
|
|
|
|
|
|
|
|
} // Predicates = [HasAtomics]
|
|
|
|
|
|
|
|
// Truncating stores.
|
2019-02-20 09:29:34 +08:00
|
|
|
defm ATOMIC_STORE8_I32 : AtomicStore<I32, "i32.atomic.store8", 0x19>;
|
|
|
|
defm ATOMIC_STORE16_I32 : AtomicStore<I32, "i32.atomic.store16", 0x1a>;
|
|
|
|
defm ATOMIC_STORE8_I64 : AtomicStore<I64, "i64.atomic.store8", 0x1b>;
|
|
|
|
defm ATOMIC_STORE16_I64 : AtomicStore<I64, "i64.atomic.store16", 0x1c>;
|
|
|
|
defm ATOMIC_STORE32_I64 : AtomicStore<I64, "i64.atomic.store32", 0x1d>;
|
2018-07-03 05:22:59 +08:00
|
|
|
|
|
|
|
// Fragments for truncating stores.
|
|
|
|
|
|
|
|
// We don't have single truncating atomic store instructions. For 32-bit
|
|
|
|
// instructions, we just need to match bare atomic stores. On the other hand,
|
|
|
|
// truncating stores from i64 values are once truncated to i32 first.
|
2018-07-10 04:18:21 +08:00
|
|
|
class trunc_astore_64<PatFrag kind> :
|
2018-07-03 05:22:59 +08:00
|
|
|
PatFrag<(ops node:$addr, node:$val),
|
2018-07-10 04:18:21 +08:00
|
|
|
(kind node:$addr, (i32 (trunc (i64 node:$val))))>;
|
2018-07-03 05:22:59 +08:00
|
|
|
def trunc_astore_8_64 : trunc_astore_64<atomic_store_8>;
|
|
|
|
def trunc_astore_16_64 : trunc_astore_64<atomic_store_16>;
|
|
|
|
def trunc_astore_32_64 : trunc_astore_64<atomic_store_32>;
|
|
|
|
|
|
|
|
let Predicates = [HasAtomics] in {
|
|
|
|
|
|
|
|
// Truncating stores with no constant offset
|
|
|
|
def : AStorePatNoOffset<i32, atomic_store_8, ATOMIC_STORE8_I32>;
|
|
|
|
def : AStorePatNoOffset<i32, atomic_store_16, ATOMIC_STORE16_I32>;
|
|
|
|
def : AStorePatNoOffset<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
|
|
|
|
def : AStorePatNoOffset<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
|
|
|
|
def : AStorePatNoOffset<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
|
|
|
|
|
|
|
|
// Truncating stores with a constant offset
|
|
|
|
def : AStorePatImmOff<i32, atomic_store_8, regPlusImm, ATOMIC_STORE8_I32>;
|
|
|
|
def : AStorePatImmOff<i32, atomic_store_16, regPlusImm, ATOMIC_STORE16_I32>;
|
|
|
|
def : AStorePatImmOff<i64, trunc_astore_8_64, regPlusImm, ATOMIC_STORE8_I64>;
|
|
|
|
def : AStorePatImmOff<i64, trunc_astore_16_64, regPlusImm, ATOMIC_STORE16_I64>;
|
|
|
|
def : AStorePatImmOff<i64, trunc_astore_32_64, regPlusImm, ATOMIC_STORE32_I64>;
|
|
|
|
def : AStorePatImmOff<i32, atomic_store_8, or_is_add, ATOMIC_STORE8_I32>;
|
|
|
|
def : AStorePatImmOff<i32, atomic_store_16, or_is_add, ATOMIC_STORE16_I32>;
|
|
|
|
def : AStorePatImmOff<i64, trunc_astore_8_64, or_is_add, ATOMIC_STORE8_I64>;
|
|
|
|
def : AStorePatImmOff<i64, trunc_astore_16_64, or_is_add, ATOMIC_STORE16_I64>;
|
|
|
|
def : AStorePatImmOff<i64, trunc_astore_32_64, or_is_add, ATOMIC_STORE32_I64>;
|
|
|
|
|
|
|
|
def : AStorePatGlobalAddr<i32, atomic_store_8, ATOMIC_STORE8_I32>;
|
|
|
|
def : AStorePatGlobalAddr<i32, atomic_store_16, ATOMIC_STORE16_I32>;
|
|
|
|
def : AStorePatGlobalAddr<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
|
|
|
|
def : AStorePatGlobalAddr<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
|
|
|
|
def : AStorePatGlobalAddr<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
|
|
|
|
|
|
|
|
// Truncating stores with just a constant offset
|
|
|
|
def : AStorePatOffsetOnly<i32, atomic_store_8, ATOMIC_STORE8_I32>;
|
|
|
|
def : AStorePatOffsetOnly<i32, atomic_store_16, ATOMIC_STORE16_I32>;
|
|
|
|
def : AStorePatOffsetOnly<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
|
|
|
|
def : AStorePatOffsetOnly<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
|
|
|
|
def : AStorePatOffsetOnly<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
|
|
|
|
|
|
|
|
def : AStorePatGlobalAddrOffOnly<i32, atomic_store_8, ATOMIC_STORE8_I32>;
|
|
|
|
def : AStorePatGlobalAddrOffOnly<i32, atomic_store_16, ATOMIC_STORE16_I32>;
|
|
|
|
def : AStorePatGlobalAddrOffOnly<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>;
|
|
|
|
def : AStorePatGlobalAddrOffOnly<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>;
|
|
|
|
def : AStorePatGlobalAddrOffOnly<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
|
|
|
|
|
|
|
|
} // Predicates = [HasAtomics]
|
2015-06-30 07:51:55 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
// Atomic binary read-modify-writes
|
2015-06-30 07:51:55 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2019-02-20 09:29:34 +08:00
|
|
|
multiclass WebAssemblyBinRMW<WebAssemblyRegClass rc, string name,
|
|
|
|
int atomic_op> {
|
|
|
|
defm "" :
|
|
|
|
ATOMIC_I<(outs rc:$dst),
|
|
|
|
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$val),
|
|
|
|
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
|
|
|
|
!strconcat(name, "\t$dst, ${off}(${addr})${p2align}, $val"),
|
|
|
|
!strconcat(name, "\t${off}${p2align}"), atomic_op>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
}
|
|
|
|
|
2019-02-20 09:29:34 +08:00
|
|
|
defm ATOMIC_RMW_ADD_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.add", 0x1e>;
|
|
|
|
defm ATOMIC_RMW_ADD_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.add", 0x1f>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW8_U_ADD_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.add_u", 0x20>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW16_U_ADD_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.add_u", 0x21>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW8_U_ADD_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.add_u", 0x22>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW16_U_ADD_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.add_u", 0x23>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW32_U_ADD_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.add_u", 0x24>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
|
2019-02-20 09:29:34 +08:00
|
|
|
defm ATOMIC_RMW_SUB_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.sub", 0x25>;
|
|
|
|
defm ATOMIC_RMW_SUB_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.sub", 0x26>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW8_U_SUB_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.sub_u", 0x27>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW16_U_SUB_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.sub_u", 0x28>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW8_U_SUB_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.sub_u", 0x29>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW16_U_SUB_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.sub_u", 0x2a>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW32_U_SUB_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.sub_u", 0x2b>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
|
2019-02-20 09:29:34 +08:00
|
|
|
defm ATOMIC_RMW_AND_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.and", 0x2c>;
|
|
|
|
defm ATOMIC_RMW_AND_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.and", 0x2d>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW8_U_AND_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.and_u", 0x2e>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW16_U_AND_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.and_u", 0x2f>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW8_U_AND_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.and_u", 0x30>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW16_U_AND_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.and_u", 0x31>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW32_U_AND_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.and_u", 0x32>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
|
2019-02-20 09:29:34 +08:00
|
|
|
defm ATOMIC_RMW_OR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.or", 0x33>;
|
|
|
|
defm ATOMIC_RMW_OR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.or", 0x34>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW8_U_OR_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.or_u", 0x35>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW16_U_OR_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.or_u", 0x36>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW8_U_OR_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.or_u", 0x37>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW16_U_OR_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.or_u", 0x38>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW32_U_OR_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.or_u", 0x39>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
|
2019-02-20 09:29:34 +08:00
|
|
|
defm ATOMIC_RMW_XOR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.xor", 0x3a>;
|
|
|
|
defm ATOMIC_RMW_XOR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.xor", 0x3b>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW8_U_XOR_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xor_u", 0x3c>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW16_U_XOR_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xor_u", 0x3d>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW8_U_XOR_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xor_u", 0x3e>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW16_U_XOR_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xor_u", 0x3f>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW32_U_XOR_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xor_u", 0x40>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
|
|
|
|
defm ATOMIC_RMW_XCHG_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw.xchg", 0x41>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW_XCHG_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw.xchg", 0x42>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW8_U_XCHG_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xchg_u", 0x43>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW16_U_XCHG_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xchg_u", 0x44>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW8_U_XCHG_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xchg_u", 0x45>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW16_U_XCHG_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xchg_u", 0x46>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
defm ATOMIC_RMW32_U_XCHG_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xchg_u", 0x47>;
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
|
|
|
|
// Select binary RMWs with no constant offset.
|
|
|
|
class BinRMWPatNoOffset<ValueType ty, PatFrag kind, NI inst> :
|
|
|
|
Pat<(ty (kind I32:$addr, ty:$val)), (inst 0, 0, I32:$addr, ty:$val)>;
|
|
|
|
|
|
|
|
// Select binary RMWs with a constant offset.
|
|
|
|
|
|
|
|
// Pattern with address + immediate offset
|
|
|
|
class BinRMWPatImmOff<ValueType ty, PatFrag kind, PatFrag operand, NI inst> :
|
|
|
|
Pat<(ty (kind (operand I32:$addr, imm:$off), ty:$val)),
|
|
|
|
(inst 0, imm:$off, I32:$addr, ty:$val)>;
|
|
|
|
|
|
|
|
class BinRMWPatGlobalAddr<ValueType ty, PatFrag kind, NI inst> :
|
|
|
|
Pat<(ty (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
|
|
|
|
ty:$val)),
|
|
|
|
(inst 0, tglobaladdr:$off, I32:$addr, ty:$val)>;
|
|
|
|
|
|
|
|
// Select binary RMWs with just a constant offset.
|
|
|
|
class BinRMWPatOffsetOnly<ValueType ty, PatFrag kind, NI inst> :
|
|
|
|
Pat<(ty (kind imm:$off, ty:$val)),
|
|
|
|
(inst 0, imm:$off, (CONST_I32 0), ty:$val)>;
|
|
|
|
|
|
|
|
class BinRMWPatGlobalAddrOffOnly<ValueType ty, PatFrag kind, NI inst> :
|
|
|
|
Pat<(ty (kind (WebAssemblywrapper tglobaladdr:$off), ty:$val)),
|
|
|
|
(inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$val)>;
|
|
|
|
|
|
|
|
// Patterns for various addressing modes.
|
|
|
|
multiclass BinRMWPattern<PatFrag rmw_32, PatFrag rmw_64, NI inst_32,
|
|
|
|
NI inst_64> {
|
|
|
|
def : BinRMWPatNoOffset<i32, rmw_32, inst_32>;
|
|
|
|
def : BinRMWPatNoOffset<i64, rmw_64, inst_64>;
|
2015-06-30 07:51:55 +08:00
|
|
|
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
def : BinRMWPatImmOff<i32, rmw_32, regPlusImm, inst_32>;
|
|
|
|
def : BinRMWPatImmOff<i64, rmw_64, regPlusImm, inst_64>;
|
|
|
|
def : BinRMWPatImmOff<i32, rmw_32, or_is_add, inst_32>;
|
|
|
|
def : BinRMWPatImmOff<i64, rmw_64, or_is_add, inst_64>;
|
2015-06-30 07:51:55 +08:00
|
|
|
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
def : BinRMWPatGlobalAddr<i32, rmw_32, inst_32>;
|
|
|
|
def : BinRMWPatGlobalAddr<i64, rmw_64, inst_64>;
|
2015-06-30 07:51:55 +08:00
|
|
|
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
def : BinRMWPatOffsetOnly<i32, rmw_32, inst_32>;
|
|
|
|
def : BinRMWPatOffsetOnly<i64, rmw_64, inst_64>;
|
2017-08-31 02:07:45 +08:00
|
|
|
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
def : BinRMWPatGlobalAddrOffOnly<i32, rmw_32, inst_32>;
|
|
|
|
def : BinRMWPatGlobalAddrOffOnly<i64, rmw_64, inst_64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
let Predicates = [HasAtomics] in {
|
|
|
|
defm : BinRMWPattern<atomic_load_add_32, atomic_load_add_64, ATOMIC_RMW_ADD_I32,
|
|
|
|
ATOMIC_RMW_ADD_I64>;
|
|
|
|
defm : BinRMWPattern<atomic_load_sub_32, atomic_load_sub_64, ATOMIC_RMW_SUB_I32,
|
|
|
|
ATOMIC_RMW_SUB_I64>;
|
|
|
|
defm : BinRMWPattern<atomic_load_and_32, atomic_load_and_64, ATOMIC_RMW_AND_I32,
|
|
|
|
ATOMIC_RMW_AND_I64>;
|
|
|
|
defm : BinRMWPattern<atomic_load_or_32, atomic_load_or_64, ATOMIC_RMW_OR_I32,
|
|
|
|
ATOMIC_RMW_OR_I64>;
|
|
|
|
defm : BinRMWPattern<atomic_load_xor_32, atomic_load_xor_64, ATOMIC_RMW_XOR_I32,
|
|
|
|
ATOMIC_RMW_XOR_I64>;
|
|
|
|
defm : BinRMWPattern<atomic_swap_32, atomic_swap_64, ATOMIC_RMW_XCHG_I32,
|
|
|
|
ATOMIC_RMW_XCHG_I64>;
|
|
|
|
} // Predicates = [HasAtomics]
|
|
|
|
|
|
|
|
// Truncating & zero-extending binary RMW patterns.
|
|
|
|
// These are combined patterns of truncating store patterns and zero-extending
|
|
|
|
// load patterns above.
|
|
|
|
class zext_bin_rmw_8_32<PatFrag kind> :
|
|
|
|
PatFrag<(ops node:$addr, node:$val),
|
|
|
|
(and (i32 (kind node:$addr, node:$val)), 255)>;
|
|
|
|
class zext_bin_rmw_16_32<PatFrag kind> :
|
|
|
|
PatFrag<(ops node:$addr, node:$val),
|
|
|
|
(and (i32 (kind node:$addr, node:$val)), 65535)>;
|
|
|
|
class zext_bin_rmw_8_64<PatFrag kind> :
|
|
|
|
PatFrag<(ops node:$addr, node:$val),
|
|
|
|
(and (i64 (anyext (i32 (kind node:$addr,
|
|
|
|
(i32 (trunc (i64 node:$val))))))), 255)>;
|
|
|
|
class zext_bin_rmw_16_64<PatFrag kind> :
|
|
|
|
PatFrag<(ops node:$addr, node:$val),
|
|
|
|
(and (i64 (anyext (i32 (kind node:$addr,
|
|
|
|
(i32 (trunc (i64 node:$val))))))), 65535)>;
|
|
|
|
class zext_bin_rmw_32_64<PatFrag kind> :
|
|
|
|
PatFrag<(ops node:$addr, node:$val),
|
|
|
|
(zext (i32 (kind node:$addr, (i32 (trunc (i64 node:$val))))))>;
|
|
|
|
|
|
|
|
// Truncating & sign-extending binary RMW patterns.
|
|
|
|
// These are combined patterns of truncating store patterns and sign-extending
|
|
|
|
// load patterns above. We match subword RMWs (for 32-bit) and anyext RMWs (for
|
|
|
|
// 64-bit) and select a zext RMW; the next instruction will be sext_inreg which
|
|
|
|
// is selected by itself.
|
|
|
|
class sext_bin_rmw_8_32<PatFrag kind> :
|
|
|
|
PatFrag<(ops node:$addr, node:$val), (kind node:$addr, node:$val)>;
|
|
|
|
class sext_bin_rmw_16_32<PatFrag kind> : sext_bin_rmw_8_32<kind>;
|
|
|
|
class sext_bin_rmw_8_64<PatFrag kind> :
|
|
|
|
PatFrag<(ops node:$addr, node:$val),
|
|
|
|
(anyext (i32 (kind node:$addr, (i32 (trunc (i64 node:$val))))))>;
|
|
|
|
class sext_bin_rmw_16_64<PatFrag kind> : sext_bin_rmw_8_64<kind>;
|
2019-01-08 14:25:55 +08:00
|
|
|
// 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s
|
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
2018-07-10 06:30:51 +08:00
|
|
|
|
|
|
|
// Patterns for various addressing modes for truncating-extending binary RMWs.
|
|
|
|
multiclass BinRMWTruncExtPattern<
|
|
|
|
PatFrag rmw_8, PatFrag rmw_16, PatFrag rmw_32, PatFrag rmw_64,
|
|
|
|
NI inst8_32, NI inst16_32, NI inst8_64, NI inst16_64, NI inst32_64> {
|
|
|
|
// Truncating-extending binary RMWs with no constant offset
|
|
|
|
def : BinRMWPatNoOffset<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : BinRMWPatNoOffset<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : BinRMWPatNoOffset<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : BinRMWPatNoOffset<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
def : BinRMWPatNoOffset<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>;
|
|
|
|
|
|
|
|
def : BinRMWPatNoOffset<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : BinRMWPatNoOffset<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : BinRMWPatNoOffset<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : BinRMWPatNoOffset<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
|
|
|
|
// Truncating-extending binary RMWs with a constant offset
|
|
|
|
def : BinRMWPatImmOff<i32, zext_bin_rmw_8_32<rmw_8>, regPlusImm, inst8_32>;
|
|
|
|
def : BinRMWPatImmOff<i32, zext_bin_rmw_16_32<rmw_16>, regPlusImm, inst16_32>;
|
|
|
|
def : BinRMWPatImmOff<i64, zext_bin_rmw_8_64<rmw_8>, regPlusImm, inst8_64>;
|
|
|
|
def : BinRMWPatImmOff<i64, zext_bin_rmw_16_64<rmw_16>, regPlusImm, inst16_64>;
|
|
|
|
def : BinRMWPatImmOff<i64, zext_bin_rmw_32_64<rmw_32>, regPlusImm, inst32_64>;
|
|
|
|
def : BinRMWPatImmOff<i32, zext_bin_rmw_8_32<rmw_8>, or_is_add, inst8_32>;
|
|
|
|
def : BinRMWPatImmOff<i32, zext_bin_rmw_16_32<rmw_16>, or_is_add, inst16_32>;
|
|
|
|
def : BinRMWPatImmOff<i64, zext_bin_rmw_8_64<rmw_8>, or_is_add, inst8_64>;
|
|
|
|
def : BinRMWPatImmOff<i64, zext_bin_rmw_16_64<rmw_16>, or_is_add, inst16_64>;
|
|
|
|
def : BinRMWPatImmOff<i64, zext_bin_rmw_32_64<rmw_32>, or_is_add, inst32_64>;
|
|
|
|
|
|
|
|
def : BinRMWPatImmOff<i32, sext_bin_rmw_8_32<rmw_8>, regPlusImm, inst8_32>;
|
|
|
|
def : BinRMWPatImmOff<i32, sext_bin_rmw_16_32<rmw_16>, regPlusImm, inst16_32>;
|
|
|
|
def : BinRMWPatImmOff<i64, sext_bin_rmw_8_64<rmw_8>, regPlusImm, inst8_64>;
|
|
|
|
def : BinRMWPatImmOff<i64, sext_bin_rmw_16_64<rmw_16>, regPlusImm, inst16_64>;
|
|
|
|
def : BinRMWPatImmOff<i32, sext_bin_rmw_8_32<rmw_8>, or_is_add, inst8_32>;
|
|
|
|
def : BinRMWPatImmOff<i32, sext_bin_rmw_16_32<rmw_16>, or_is_add, inst16_32>;
|
|
|
|
def : BinRMWPatImmOff<i64, sext_bin_rmw_8_64<rmw_8>, or_is_add, inst8_64>;
|
|
|
|
def : BinRMWPatImmOff<i64, sext_bin_rmw_16_64<rmw_16>, or_is_add, inst16_64>;
|
|
|
|
|
|
|
|
def : BinRMWPatGlobalAddr<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : BinRMWPatGlobalAddr<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : BinRMWPatGlobalAddr<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : BinRMWPatGlobalAddr<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
def : BinRMWPatGlobalAddr<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>;
|
|
|
|
|
|
|
|
def : BinRMWPatGlobalAddr<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : BinRMWPatGlobalAddr<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : BinRMWPatGlobalAddr<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : BinRMWPatGlobalAddr<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
|
|
|
|
// Truncating-extending binary RMWs with just a constant offset
|
|
|
|
def : BinRMWPatOffsetOnly<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : BinRMWPatOffsetOnly<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : BinRMWPatOffsetOnly<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : BinRMWPatOffsetOnly<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
def : BinRMWPatOffsetOnly<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>;
|
|
|
|
|
|
|
|
def : BinRMWPatOffsetOnly<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : BinRMWPatOffsetOnly<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : BinRMWPatOffsetOnly<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : BinRMWPatOffsetOnly<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
|
|
|
|
def : BinRMWPatGlobalAddrOffOnly<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : BinRMWPatGlobalAddrOffOnly<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : BinRMWPatGlobalAddrOffOnly<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : BinRMWPatGlobalAddrOffOnly<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
def : BinRMWPatGlobalAddrOffOnly<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>;
|
|
|
|
|
|
|
|
def : BinRMWPatGlobalAddrOffOnly<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : BinRMWPatGlobalAddrOffOnly<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : BinRMWPatGlobalAddrOffOnly<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : BinRMWPatGlobalAddrOffOnly<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
let Predicates = [HasAtomics] in {
|
|
|
|
defm : BinRMWTruncExtPattern<
|
|
|
|
atomic_load_add_8, atomic_load_add_16, atomic_load_add_32, atomic_load_add_64,
|
|
|
|
ATOMIC_RMW8_U_ADD_I32, ATOMIC_RMW16_U_ADD_I32,
|
|
|
|
ATOMIC_RMW8_U_ADD_I64, ATOMIC_RMW16_U_ADD_I64, ATOMIC_RMW32_U_ADD_I64>;
|
|
|
|
defm : BinRMWTruncExtPattern<
|
|
|
|
atomic_load_sub_8, atomic_load_sub_16, atomic_load_sub_32, atomic_load_sub_64,
|
|
|
|
ATOMIC_RMW8_U_SUB_I32, ATOMIC_RMW16_U_SUB_I32,
|
|
|
|
ATOMIC_RMW8_U_SUB_I64, ATOMIC_RMW16_U_SUB_I64, ATOMIC_RMW32_U_SUB_I64>;
|
|
|
|
defm : BinRMWTruncExtPattern<
|
|
|
|
atomic_load_and_8, atomic_load_and_16, atomic_load_and_32, atomic_load_and_64,
|
|
|
|
ATOMIC_RMW8_U_AND_I32, ATOMIC_RMW16_U_AND_I32,
|
|
|
|
ATOMIC_RMW8_U_AND_I64, ATOMIC_RMW16_U_AND_I64, ATOMIC_RMW32_U_AND_I64>;
|
|
|
|
defm : BinRMWTruncExtPattern<
|
|
|
|
atomic_load_or_8, atomic_load_or_16, atomic_load_or_32, atomic_load_or_64,
|
|
|
|
ATOMIC_RMW8_U_OR_I32, ATOMIC_RMW16_U_OR_I32,
|
|
|
|
ATOMIC_RMW8_U_OR_I64, ATOMIC_RMW16_U_OR_I64, ATOMIC_RMW32_U_OR_I64>;
|
|
|
|
defm : BinRMWTruncExtPattern<
|
|
|
|
atomic_load_xor_8, atomic_load_xor_16, atomic_load_xor_32, atomic_load_xor_64,
|
|
|
|
ATOMIC_RMW8_U_XOR_I32, ATOMIC_RMW16_U_XOR_I32,
|
|
|
|
ATOMIC_RMW8_U_XOR_I64, ATOMIC_RMW16_U_XOR_I64, ATOMIC_RMW32_U_XOR_I64>;
|
|
|
|
defm : BinRMWTruncExtPattern<
|
|
|
|
atomic_swap_8, atomic_swap_16, atomic_swap_32, atomic_swap_64,
|
|
|
|
ATOMIC_RMW8_U_XCHG_I32, ATOMIC_RMW16_U_XCHG_I32,
|
|
|
|
ATOMIC_RMW8_U_XCHG_I64, ATOMIC_RMW16_U_XCHG_I64, ATOMIC_RMW32_U_XCHG_I64>;
|
|
|
|
} // Predicates = [HasAtomics]
|
2018-08-02 03:40:28 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Atomic ternary read-modify-writes
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2018-08-07 08:22:22 +08:00
|
|
|
// TODO LLVM IR's cmpxchg instruction returns a pair of {loaded value, success
|
|
|
|
// flag}. When we use the success flag or both values, we can't make use of i64
|
|
|
|
// truncate/extend versions of instructions for now, which is suboptimal.
|
|
|
|
// Consider adding a pass after instruction selection that optimizes this case
|
|
|
|
// if it is frequent.
|
2018-08-02 03:40:28 +08:00
|
|
|
|
2019-02-20 09:29:34 +08:00
|
|
|
multiclass WebAssemblyTerRMW<WebAssemblyRegClass rc, string name,
|
|
|
|
int atomic_op> {
|
|
|
|
defm "" :
|
|
|
|
ATOMIC_I<(outs rc:$dst),
|
|
|
|
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$exp,
|
[WebAssembly] Use named operands to identify loads and stores
Summary:
Uses the named operands tablegen feature to look up the indices of
offset, address, and p2align operands for all load and store
instructions. This replaces brittle, incorrect logic for identifying
loads and store when eliminating frame indices, which previously
crashed on bulk-memory ops. It also cleans up the SetP2Alignment pass.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59007
llvm-svn: 355770
2019-03-09 12:31:37 +08:00
|
|
|
rc:$new_),
|
2019-02-20 09:29:34 +08:00
|
|
|
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
|
[WebAssembly] Use named operands to identify loads and stores
Summary:
Uses the named operands tablegen feature to look up the indices of
offset, address, and p2align operands for all load and store
instructions. This replaces brittle, incorrect logic for identifying
loads and store when eliminating frame indices, which previously
crashed on bulk-memory ops. It also cleans up the SetP2Alignment pass.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59007
llvm-svn: 355770
2019-03-09 12:31:37 +08:00
|
|
|
!strconcat(name, "\t$dst, ${off}(${addr})${p2align}, $exp, $new_"),
|
2019-02-20 09:29:34 +08:00
|
|
|
!strconcat(name, "\t${off}${p2align}"), atomic_op>;
|
2018-08-02 03:40:28 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
defm ATOMIC_RMW_CMPXCHG_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyTerRMW<I32, "i32.atomic.rmw.cmpxchg", 0x48>;
|
2018-08-02 03:40:28 +08:00
|
|
|
defm ATOMIC_RMW_CMPXCHG_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyTerRMW<I64, "i64.atomic.rmw.cmpxchg", 0x49>;
|
2018-08-02 03:40:28 +08:00
|
|
|
defm ATOMIC_RMW8_U_CMPXCHG_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyTerRMW<I32, "i32.atomic.rmw8.cmpxchg_u", 0x4a>;
|
2018-08-02 03:40:28 +08:00
|
|
|
defm ATOMIC_RMW16_U_CMPXCHG_I32 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyTerRMW<I32, "i32.atomic.rmw16.cmpxchg_u", 0x4b>;
|
2018-08-02 03:40:28 +08:00
|
|
|
defm ATOMIC_RMW8_U_CMPXCHG_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyTerRMW<I64, "i64.atomic.rmw8.cmpxchg_u", 0x4c>;
|
2018-08-02 03:40:28 +08:00
|
|
|
defm ATOMIC_RMW16_U_CMPXCHG_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyTerRMW<I64, "i64.atomic.rmw16.cmpxchg_u", 0x4d>;
|
2018-08-02 03:40:28 +08:00
|
|
|
defm ATOMIC_RMW32_U_CMPXCHG_I64 :
|
2019-02-20 09:29:34 +08:00
|
|
|
WebAssemblyTerRMW<I64, "i64.atomic.rmw32.cmpxchg_u", 0x4e>;
|
2018-08-02 03:40:28 +08:00
|
|
|
|
|
|
|
// Select ternary RMWs with no constant offset.
|
|
|
|
class TerRMWPatNoOffset<ValueType ty, PatFrag kind, NI inst> :
|
|
|
|
Pat<(ty (kind I32:$addr, ty:$exp, ty:$new)),
|
|
|
|
(inst 0, 0, I32:$addr, ty:$exp, ty:$new)>;
|
|
|
|
|
|
|
|
// Select ternary RMWs with a constant offset.
|
|
|
|
|
|
|
|
// Pattern with address + immediate offset
|
|
|
|
class TerRMWPatImmOff<ValueType ty, PatFrag kind, PatFrag operand, NI inst> :
|
|
|
|
Pat<(ty (kind (operand I32:$addr, imm:$off), ty:$exp, ty:$new)),
|
|
|
|
(inst 0, imm:$off, I32:$addr, ty:$exp, ty:$new)>;
|
|
|
|
|
|
|
|
class TerRMWPatGlobalAddr<ValueType ty, PatFrag kind, NI inst> :
|
|
|
|
Pat<(ty (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
|
|
|
|
ty:$exp, ty:$new)),
|
|
|
|
(inst 0, tglobaladdr:$off, I32:$addr, ty:$exp, ty:$new)>;
|
|
|
|
|
|
|
|
// Select ternary RMWs with just a constant offset.
|
|
|
|
class TerRMWPatOffsetOnly<ValueType ty, PatFrag kind, NI inst> :
|
|
|
|
Pat<(ty (kind imm:$off, ty:$exp, ty:$new)),
|
|
|
|
(inst 0, imm:$off, (CONST_I32 0), ty:$exp, ty:$new)>;
|
|
|
|
|
|
|
|
class TerRMWPatGlobalAddrOffOnly<ValueType ty, PatFrag kind, NI inst> :
|
|
|
|
Pat<(ty (kind (WebAssemblywrapper tglobaladdr:$off), ty:$exp, ty:$new)),
|
|
|
|
(inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$exp, ty:$new)>;
|
|
|
|
|
|
|
|
// Patterns for various addressing modes.
|
|
|
|
multiclass TerRMWPattern<PatFrag rmw_32, PatFrag rmw_64, NI inst_32,
|
|
|
|
NI inst_64> {
|
|
|
|
def : TerRMWPatNoOffset<i32, rmw_32, inst_32>;
|
|
|
|
def : TerRMWPatNoOffset<i64, rmw_64, inst_64>;
|
|
|
|
|
|
|
|
def : TerRMWPatImmOff<i32, rmw_32, regPlusImm, inst_32>;
|
|
|
|
def : TerRMWPatImmOff<i64, rmw_64, regPlusImm, inst_64>;
|
|
|
|
def : TerRMWPatImmOff<i32, rmw_32, or_is_add, inst_32>;
|
|
|
|
def : TerRMWPatImmOff<i64, rmw_64, or_is_add, inst_64>;
|
|
|
|
|
|
|
|
def : TerRMWPatGlobalAddr<i32, rmw_32, inst_32>;
|
|
|
|
def : TerRMWPatGlobalAddr<i64, rmw_64, inst_64>;
|
|
|
|
|
|
|
|
def : TerRMWPatOffsetOnly<i32, rmw_32, inst_32>;
|
|
|
|
def : TerRMWPatOffsetOnly<i64, rmw_64, inst_64>;
|
|
|
|
|
|
|
|
def : TerRMWPatGlobalAddrOffOnly<i32, rmw_32, inst_32>;
|
|
|
|
def : TerRMWPatGlobalAddrOffOnly<i64, rmw_64, inst_64>;
|
|
|
|
}
|
|
|
|
|
2019-02-06 08:17:03 +08:00
|
|
|
let Predicates = [HasAtomics] in
|
2018-08-02 03:40:28 +08:00
|
|
|
defm : TerRMWPattern<atomic_cmp_swap_32, atomic_cmp_swap_64,
|
|
|
|
ATOMIC_RMW_CMPXCHG_I32, ATOMIC_RMW_CMPXCHG_I64>;
|
|
|
|
|
|
|
|
// Truncating & zero-extending ternary RMW patterns.
|
|
|
|
// DAG legalization & optimization before instruction selection may introduce
|
|
|
|
// additional nodes such as anyext or assertzext depending on operand types.
|
|
|
|
class zext_ter_rmw_8_32<PatFrag kind> :
|
|
|
|
PatFrag<(ops node:$addr, node:$exp, node:$new),
|
|
|
|
(and (i32 (kind node:$addr, node:$exp, node:$new)), 255)>;
|
|
|
|
class zext_ter_rmw_16_32<PatFrag kind> :
|
|
|
|
PatFrag<(ops node:$addr, node:$exp, node:$new),
|
|
|
|
(and (i32 (kind node:$addr, node:$exp, node:$new)), 65535)>;
|
|
|
|
class zext_ter_rmw_8_64<PatFrag kind> :
|
|
|
|
PatFrag<(ops node:$addr, node:$exp, node:$new),
|
|
|
|
(zext (i32 (assertzext (i32 (kind node:$addr,
|
|
|
|
(i32 (trunc (i64 node:$exp))),
|
|
|
|
(i32 (trunc (i64 node:$new))))))))>;
|
|
|
|
class zext_ter_rmw_16_64<PatFrag kind> : zext_ter_rmw_8_64<kind>;
|
|
|
|
class zext_ter_rmw_32_64<PatFrag kind> :
|
|
|
|
PatFrag<(ops node:$addr, node:$exp, node:$new),
|
|
|
|
(zext (i32 (kind node:$addr,
|
|
|
|
(i32 (trunc (i64 node:$exp))),
|
|
|
|
(i32 (trunc (i64 node:$new))))))>;
|
|
|
|
|
|
|
|
// Truncating & sign-extending ternary RMW patterns.
|
|
|
|
// We match subword RMWs (for 32-bit) and anyext RMWs (for 64-bit) and select a
|
|
|
|
// zext RMW; the next instruction will be sext_inreg which is selected by
|
|
|
|
// itself.
|
|
|
|
class sext_ter_rmw_8_32<PatFrag kind> :
|
|
|
|
PatFrag<(ops node:$addr, node:$exp, node:$new),
|
|
|
|
(kind node:$addr, node:$exp, node:$new)>;
|
|
|
|
class sext_ter_rmw_16_32<PatFrag kind> : sext_ter_rmw_8_32<kind>;
|
|
|
|
class sext_ter_rmw_8_64<PatFrag kind> :
|
|
|
|
PatFrag<(ops node:$addr, node:$exp, node:$new),
|
|
|
|
(anyext (i32 (assertzext (i32
|
|
|
|
(kind node:$addr,
|
|
|
|
(i32 (trunc (i64 node:$exp))),
|
|
|
|
(i32 (trunc (i64 node:$new))))))))>;
|
|
|
|
class sext_ter_rmw_16_64<PatFrag kind> : sext_ter_rmw_8_64<kind>;
|
2019-01-08 14:25:55 +08:00
|
|
|
// 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s
|
2018-08-02 03:40:28 +08:00
|
|
|
|
|
|
|
// Patterns for various addressing modes for truncating-extending ternary RMWs.
|
|
|
|
multiclass TerRMWTruncExtPattern<
|
|
|
|
PatFrag rmw_8, PatFrag rmw_16, PatFrag rmw_32, PatFrag rmw_64,
|
|
|
|
NI inst8_32, NI inst16_32, NI inst8_64, NI inst16_64, NI inst32_64> {
|
|
|
|
// Truncating-extending ternary RMWs with no constant offset
|
|
|
|
def : TerRMWPatNoOffset<i32, zext_ter_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : TerRMWPatNoOffset<i32, zext_ter_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : TerRMWPatNoOffset<i64, zext_ter_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : TerRMWPatNoOffset<i64, zext_ter_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
def : TerRMWPatNoOffset<i64, zext_ter_rmw_32_64<rmw_32>, inst32_64>;
|
|
|
|
|
|
|
|
def : TerRMWPatNoOffset<i32, sext_ter_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : TerRMWPatNoOffset<i32, sext_ter_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : TerRMWPatNoOffset<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : TerRMWPatNoOffset<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
|
|
|
|
// Truncating-extending ternary RMWs with a constant offset
|
|
|
|
def : TerRMWPatImmOff<i32, zext_ter_rmw_8_32<rmw_8>, regPlusImm, inst8_32>;
|
|
|
|
def : TerRMWPatImmOff<i32, zext_ter_rmw_16_32<rmw_16>, regPlusImm, inst16_32>;
|
|
|
|
def : TerRMWPatImmOff<i64, zext_ter_rmw_8_64<rmw_8>, regPlusImm, inst8_64>;
|
|
|
|
def : TerRMWPatImmOff<i64, zext_ter_rmw_16_64<rmw_16>, regPlusImm, inst16_64>;
|
|
|
|
def : TerRMWPatImmOff<i64, zext_ter_rmw_32_64<rmw_32>, regPlusImm, inst32_64>;
|
|
|
|
def : TerRMWPatImmOff<i32, zext_ter_rmw_8_32<rmw_8>, or_is_add, inst8_32>;
|
|
|
|
def : TerRMWPatImmOff<i32, zext_ter_rmw_16_32<rmw_16>, or_is_add, inst16_32>;
|
|
|
|
def : TerRMWPatImmOff<i64, zext_ter_rmw_8_64<rmw_8>, or_is_add, inst8_64>;
|
|
|
|
def : TerRMWPatImmOff<i64, zext_ter_rmw_16_64<rmw_16>, or_is_add, inst16_64>;
|
|
|
|
def : TerRMWPatImmOff<i64, zext_ter_rmw_32_64<rmw_32>, or_is_add, inst32_64>;
|
|
|
|
|
|
|
|
def : TerRMWPatImmOff<i32, sext_ter_rmw_8_32<rmw_8>, regPlusImm, inst8_32>;
|
|
|
|
def : TerRMWPatImmOff<i32, sext_ter_rmw_16_32<rmw_16>, regPlusImm, inst16_32>;
|
|
|
|
def : TerRMWPatImmOff<i64, sext_ter_rmw_8_64<rmw_8>, regPlusImm, inst8_64>;
|
|
|
|
def : TerRMWPatImmOff<i64, sext_ter_rmw_16_64<rmw_16>, regPlusImm, inst16_64>;
|
|
|
|
def : TerRMWPatImmOff<i32, sext_ter_rmw_8_32<rmw_8>, or_is_add, inst8_32>;
|
|
|
|
def : TerRMWPatImmOff<i32, sext_ter_rmw_16_32<rmw_16>, or_is_add, inst16_32>;
|
|
|
|
def : TerRMWPatImmOff<i64, sext_ter_rmw_8_64<rmw_8>, or_is_add, inst8_64>;
|
|
|
|
def : TerRMWPatImmOff<i64, sext_ter_rmw_16_64<rmw_16>, or_is_add, inst16_64>;
|
|
|
|
|
|
|
|
def : TerRMWPatGlobalAddr<i32, zext_ter_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : TerRMWPatGlobalAddr<i32, zext_ter_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : TerRMWPatGlobalAddr<i64, zext_ter_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : TerRMWPatGlobalAddr<i64, zext_ter_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
def : TerRMWPatGlobalAddr<i64, zext_ter_rmw_32_64<rmw_32>, inst32_64>;
|
|
|
|
|
|
|
|
def : TerRMWPatGlobalAddr<i32, sext_ter_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : TerRMWPatGlobalAddr<i32, sext_ter_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : TerRMWPatGlobalAddr<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : TerRMWPatGlobalAddr<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
|
|
|
|
// Truncating-extending ternary RMWs with just a constant offset
|
|
|
|
def : TerRMWPatOffsetOnly<i32, zext_ter_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : TerRMWPatOffsetOnly<i32, zext_ter_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : TerRMWPatOffsetOnly<i64, zext_ter_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : TerRMWPatOffsetOnly<i64, zext_ter_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
def : TerRMWPatOffsetOnly<i64, zext_ter_rmw_32_64<rmw_32>, inst32_64>;
|
|
|
|
|
|
|
|
def : TerRMWPatOffsetOnly<i32, sext_ter_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : TerRMWPatOffsetOnly<i32, sext_ter_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : TerRMWPatOffsetOnly<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : TerRMWPatOffsetOnly<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
|
|
|
|
def : TerRMWPatGlobalAddrOffOnly<i32, zext_ter_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : TerRMWPatGlobalAddrOffOnly<i32, zext_ter_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : TerRMWPatGlobalAddrOffOnly<i64, zext_ter_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : TerRMWPatGlobalAddrOffOnly<i64, zext_ter_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
def : TerRMWPatGlobalAddrOffOnly<i64, zext_ter_rmw_32_64<rmw_32>, inst32_64>;
|
|
|
|
|
|
|
|
def : TerRMWPatGlobalAddrOffOnly<i32, sext_ter_rmw_8_32<rmw_8>, inst8_32>;
|
|
|
|
def : TerRMWPatGlobalAddrOffOnly<i32, sext_ter_rmw_16_32<rmw_16>, inst16_32>;
|
|
|
|
def : TerRMWPatGlobalAddrOffOnly<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>;
|
|
|
|
def : TerRMWPatGlobalAddrOffOnly<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>;
|
|
|
|
}
|
|
|
|
|
2019-02-06 08:17:03 +08:00
|
|
|
let Predicates = [HasAtomics] in
|
2018-08-02 03:40:28 +08:00
|
|
|
defm : TerRMWTruncExtPattern<
|
|
|
|
atomic_cmp_swap_8, atomic_cmp_swap_16, atomic_cmp_swap_32, atomic_cmp_swap_64,
|
|
|
|
ATOMIC_RMW8_U_CMPXCHG_I32, ATOMIC_RMW16_U_CMPXCHG_I32,
|
|
|
|
ATOMIC_RMW8_U_CMPXCHG_I64, ATOMIC_RMW16_U_CMPXCHG_I64,
|
|
|
|
ATOMIC_RMW32_U_CMPXCHG_I64>;
|